Query Regarding Implementation

Questions and discussions about the Xillybus IP core and drivers

Query Regarding Implementation

Postby Guest »

Hello,

I customized a core in IP factory, downloaded it and generated the PCIe End-point core's verilog files again in 13.1 as I'm using virtex-5. Then, I import the generated verilog files along with the top module, xillybus_ins and xillybus_core_ins to my design in ISE 14.7, where I use the design in my top module which is a schematic. The synthesis goes correctly, but when I'm implementing the design, I get an ngbuild error, saying that ISE is unable to find the xillybus_ins/xillybus_core_ins, while I'm able to see it in the heirarchy. But when I imported the xillybus_core_ins.ngc file with the xillybus_core_ins.v also in heirarchy, the design gets implemented successfully without any error. But when I compiled previous designs using the core with the demo bundle, i used only the xillybus_core_ins.v (I didn't instantiate the .ngc file), but still my design compiled.

1.) Why is this?
2.) Is this expected behaviour ?

P.S.: Also I get a warning saying that the .ngc file is for the sx50T device, can this be ignored ? or can this be changed in anyway ?

Thanks !

Mugundhan
Guest
 

Re: Query Regarding Implementation

Postby support »

Hello,

In essence, there is no need to rebuild the entire project when replacing the IP core -- just replace the .ngc file and follow the other instructions in the bundle's readme file.

Why the file wasn't found isn't clear, but it probably has to do with the search path for the .ngc file. If you managed to get the implementation through, you're good. To be extra safe, I recommend moving the file to some distant directory, and verify that the tools fail because they can't find it. Sometimes one gets the wrong file included because of misleading behavior of the search path setting.

But you've sort-of done this test already.

As for the warning you get for the ngc file, you may safely ignore it.

Regards,
Eli
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Re: Query Regarding Implementation

Postby Guest »

Hello Eli,

There is an issue when I programmed the implemented design: I'm unable to find my 4 FIFOs in my /dev folder.

Thanks,
Mugundhan
Guest
 

Re: Query Regarding Implementation

Postby support »

Hi,

If you made a change in the ngc file and Xillybus loaded properly (some device files appeared) but not as you expected, odds are that you're looking at the wrong version.

That is, either the wrong .ngc file was used during the implementation, or you loaded the wrong bitfile, or an old version's bitfile was loaded from the flash somehow.

Or some other reason for a similar confusion.

It's a bit tricky when these things happen...

Regards,
Eli
support
 
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Re: Query Regarding Implementation

Postby Guest »

Hi,

I'm able to see my fpga's pcie end point when I do lspci.

I'll try deleting the old files and implement the project again and see if I'm able to make it work.

Thank you,

Mugundhan
Guest
 

Re: Query Regarding Implementation

Postby Guest »

Hi,

Is it ok if I include the verilog file or must I include the ngc file in my project ?

Thank you,

Mugundhan
Guest
 

Re: Query Regarding Implementation

Postby support »

Hello,

In the demo bundle, the ngc files aren't included in the project. ngdbuild ("Translate") finds them automatically, as the directory in which the file is, is in the search path.

If you added the file and it works for you, it's fine as well. As long as the tools play along, it's fine. Just be sure that the correct file is loaded, if you have more than one on your hard disk.

Regards,
Eli
support
 
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