FIFO-like-behaviour of xillybus-driver?
Hello,
I'm working on a science project with the Xillybus for PCIe.
It's an Altera Stratix IV / Terasic DE4 running under Ubuntu 14.04 LTS.
What I'm currently working on involves a mechanism like this:
From a host-programm, I order the fpga to start a process that over a time creates some values.
For development sake: So far just the numbers from 1-10 for 10 clock cycles.
I want these to be written into the fifo/xillybus, so that later on and after the process, I can gather them on the host side.
What works:
"Host-reading" the xillyfile while the fpga creates the data and pushes it through the xillybus,
I "instantly" receive the numbers 1 up to 10, just as expected.
What does not work:
When I don't "host-read" the xillyfile while the data is pushed through and read from the file a few seconds later, there is no data.
I would expect to then still receive the 1-10.
Now I experimented and created 450.000.000 numbers (150MHz, so data is created and pushed for three seconds).
I manually started the read of 10 words from the xillyfile while the data is pushed, after it started, but still within the three seconds after the process-starting.
Ideally I would expect the numbers 1-10. My fifo has a depth of 1024 words with overflow protection.
What I got though were the "realtime-numbers". So after a second I would get like 150.000.000-150.000.010.
As a conclusion, to me the xillybus-driver gathers the data on the hostside in real-time and says:
"Anyone wants that newest word I just received? Yes? Take it ... No? It's gone."
What I would want it to behave is just like a fifo ... It receives everything and if I ask it for data, it first gives me its oldest data.
I thought that it also should behave like that.
Was that a misconception? If not, where could the mistake be?
Thanks and regards
Andreas