xillybus

Questions and discussions about the Xillybus IP core and drivers

xillybus

Postby Guest » Thu Jun 23, 2016 11:44 am

Respected sir

This is in reference to using HLS Vivaldo.
Please advice which version of Vivaldo to down load.
Is it ok for us to test our pcie card with xillybus core in our clients
pc for 6 months or more?

rgds.

mks
Guest
 

Re: xillybus

Postby support » Thu Jun 23, 2016 4:10 pm

Hello,

The "Getting started with the FPGA demo bundle for Xilinx" states which Vivado version is suitable for each FPGA family, but currently the limitation is version X and later, so downloading the latest is the simplest pick.

As for testing a card running Xillybus for a certain period of time, please refer to the guidelines for the Evaluation License on the Licensing page:

http://xillybus.com/licensing

If you find that your use matches the description, go ahead. If the situation isn't clear cut, I suggest dropping a mail to the e-mail address mentioned on that page, describe your situation and see if it works out.

Regards,
Eli
support
 
Posts: 590
Joined: Tue Apr 24, 2012 3:46 pm

Re: xillybus

Postby Guest » Thu Jun 30, 2016 12:33 pm

Respected sir

Successfully tested read write functions.'
Need to send digital video file data to fpga.
There two DDR3 1GB SDRAM On the pcie express board.
How to connect xillybus with DDR3 1GB SDRAM?
Is it possible to do away with these ram for smooth continuous video.
regards

mks
Guest
 

Re: xillybus

Postby support » Thu Jun 30, 2016 4:32 pm

Hello,

There is no reason to use the on-board RAMs in order to achieve a continuous video stream. Rather, the DMA buffers which Xillybus allocates automatically can be picked large enough (on the IP Core Factory) to provide for the required buffering for ensuring no overruns on the data stream.

Should you like to use the DDR memories anyhow, please consult with Xilinx' forum or support.

Regards,
Eli
support
 
Posts: 590
Joined: Tue Apr 24, 2012 3:46 pm

Re: xillybus

Postby Guest » Fri Jul 01, 2016 9:55 am

Respected sir,

Thanks.

Using the IP Factory following devices produced.

------- \\.\xillybus_read_32

Upstream (FPGA to host):
Data width: 32 bits
DMA buffers: 4 x 8 kB = 32 kB
Flow control: Asynchronous
Seekable: No

------- \\.\xillybus_write_32

Downstream (host to FPGA):
Data width: 32 bits
DMA buffers: 1024 x 512 kB = 512 MB
Flow control: Asynchronous
Seekable: No
FPGA RAM for DMA acceleration: 4 segments x 512 bytes = 2 kB


How to send 512 MB DMA data from Host to FPGA?
A sample codes sending video frames to fpga will be appreciated.
regards.

mks
Guest
 

Re: xillybus

Postby support » Sat Jul 02, 2016 8:02 am

Hello,

There is nothing special about writing data to a Xillybus stream. In essence, just issue a write() call (or Windows' WriteFile() ) whenever there is data for transmission. In a video application (which probably has a high bandwidth) you probably want to use a large buffer (32 kByte or above) for each call, so that the operating system's overhead doesn't consume too much CPU.

It's essentially as if you wanted to write the data to a file for storage, only it will appear at the FIFO in the FPGA instead.

The DMA buffers will accumulate the data that hasn't been consumed by the FPGA, so you really don't need to worry about this. With your 512 MB of buffer space, you have plenty of buffering time.

You may want to refer to section 4 ("Continuous high rate I/O") of the "Xillybus host application programming guide for Windows" in this matter.

Regards,
Eli
support
 
Posts: 590
Joined: Tue Apr 24, 2012 3:46 pm

Re: xillybus

Postby Guest » Mon Jul 04, 2016 10:00 am

Respected sir,

Thanks.
The data written from host to fpga is 32 bit wide and is written to 32 x 512 FIFO.
Is it possible to configure.
32x512 FIFO to data in 32 bit wide ( write clock as bus_clk).
8x2048 data out as 8bit wide. (read clock as 27 Mhz generated in spartan 6 )

The 8 bit data is required for Digital to Analog converter .
In case this possible suggest connection with xillybus.

regards

mks
Guest
 

Re: xillybus

Postby support » Tue Jul 05, 2016 6:24 am

Hello,

What you're looking for is an asymmetric, dual clock ("asynchronous") FIFO.

Asymmetric = it has one input of 32 bits and an output of 8 bits
Dual clock ("asynchronous") = It has one clock for read and one for write.

Xilinx' FIFOs can be configured for these parameters. Just enter the LogiCore wizard and make yourself one with FIFO generator, and use it instead of the FIFO in the demo bundle.

Regards,
Eli
support
 
Posts: 590
Joined: Tue Apr 24, 2012 3:46 pm

Re: xillybus

Postby Guest » Wed Jul 06, 2016 7:50 am

Respected Sir

Thanks for your prompt reply.
This suggestion of asymmetric, dual clock ("asynchronous") FIFO. instead of
existing FIFO in Xillybus Demo bundel. ok.
The out come this implementation will be reported to you.

mks
Guest
 

Re: xillybus

Postby Guest » Fri Jul 08, 2016 11:46 am

Respected sir,

The existing 32x504 fifo changed to 32x504 and 8x2048 fifo.
made following changes


original in xillidemo.v

// 32-bit loopback
/*
fifo_32x512 fifo_32 //write 32 bit read 32 bit
(
.clk(bus_clk),
.srst(!user_w_write_32_open && !user_r_read_32_open),
.din(user_w_write_32_data),
.wr_en(user_w_write_32_wren),
.rd_en(user_r_read_32_rden),
.dout(user_r_read_32_data),
.full(user_w_write_32_full),
.empty(user_r_read_32_empty)
);

assign user_r_read_32_eof = 0;

*/

changed to

fifo_32x512 fifo_32 //write 32bit read 8 bit
(
.rst(!user_w_write_32_open && !user_r_read_8_open), // input rst
.wr_clk(bus_clk), // input wr_clk
.rd_clk(bus_clk), // input rd_clk
.din(user_w_write_32_data), // input [31 : 0] din
.wr_en(user_w_write_32_wren), // input wr_en
.rd_en(user_r_read_8_rden), // input rd_en
.dout(user_r_read_8_data), // output [7 : 0] dout
.full(user_w_write_32_full), // output full
.empty(user_r_read_8_empty)); // output empty


assign user_r_read_8_eof = 0;

/**********************************************************************/
FIRST dos prompt
> writestream \\.\xillybus_write_32
ABCDEFGHIJKLMNOPQRSTUVWXYZ

SECOND dospromt
> readstream \\.xillybus_read_08
DCBAHGFELKJIPONMTSRQXWUV
/**********************************************************************************/

The read out is not in order
ABCD is read as DCBA
EFGH is read as HGFE and so on

FIFO write width = 32
FIFO read width = 8

kindly guide

regards

mks
Guest
 

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