xillybus

Questions and discussions about the Xillybus IP core and drivers

Re: xillybus

Postby Guest » Fri Jul 08, 2016 5:46 pm

Hello,

if you are using Xilinx FIFO generator to create you FIFO, which is the case i assume, there is nothing wrong to your readstream. Xilinx asymmetric FIFOs are design to work that way.
Find and read PG057 guide from Xilinx for more information. The easiest way to solve you problem is to rearrange the bytes of your data before storing them to the FIFO. For example
user_w_write_32_data can also been interpreted as byte0_byte1_byte2_byte3. Create an auxiliary signal, lets say temp_din, set temp_din = byte3_byte2_byte1_byte0 and then connect
temp_din to port din of the FIFO.

Regards,
John
Guest
 

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