pcie_kz_vivado_pipe_clock not found!

Questions and discussions about the Xillybus IP core and drivers

pcie_kz_vivado_pipe_clock not found!

Postby Guest » Fri Jun 24, 2016 4:21 pm

Hello,

I previously had success with the demo bundle by running the verilog .tcl and clicking generate_bitstream in vivado.

Now I have started over, this time planning to experiment with attaching my own app logic. I cleared out the project, ran the .tcl again, but this time when I try to elaborate, synthesize, or implement I receive the fatal error:

Code: Select all
[Synth 8-439] module 'pcie_k7_vivado_pipe_clock' not found ["C:/Users/sam/Desktop/xillybus-eval-virtex7-1.2d/vivado-essentials/pcie_k7_8x_pipe_clock.v":51]


Anyone know how I should address this issue or why I am now seeing this error? If I remember correctly I repeated the exact same steps from the guide which were once successful. But it's possible I'm forgetting a step.

Thank you.
Guest
 

Re: pcie_kz_vivado_pipe_clock not found!

Postby Guest » Fri Jun 24, 2016 4:53 pm

Hi again,

I appologize. You know what? I didn't clear the project entirely.

Took a look through the tcl console and saw some discrepancies about certain files, including the pipe clock file, that couldn't be loaded because they already existed. It seems the tcl script is really a one off if you don't know exactly how to modify it.

Thanks
Guest
 


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