by support »
Hello,
The reason it failed is most likely that changing the PCIe parameters may change the clock frequencies required by this Xilinx' PCIe block. In the (relatively old) revision on this block, which is used by the Xillybus bundle, this clock is generated by a module (pipe_clock) which the user logic has to instantiate and set up its parameters for. It's quite unfortunate, but that's the way it is.
The pipe_clock module is instantiated in xillybus.v, and a manual modification of the instantiation is required. The instantiation parameters PCIE_LINK_SPEED, PCIE_USERCLK1_FREQ and PCIE_USERCLK2_FREQ in particular may need an adjustment. If these aren't set correctly, odds are that the PCIe interface will not be detected at all by the computer.
The easiest way to get the correct parameters after making a change is to open a sample design of the PCIe block (in Vivado, right-click Xilinx' PCIe block's entry in the Sources view, and pick "Open IP Example Design...), and synthesize it. Then search for these names in the synthesis report, which states what those parameters should be set to. The example design should be created after changing the PCIe link parameters, of course.
It's also important to update xillydemo.xdc to reflect changes in the XDC file supplied by the example design. In fact, it might make sense to create one example design before the change, and one after, and compare them. Compare the XDC files with a diff utility, because the changes might be subtle, such as the "set_case_analysis" statements, which have a significant effect on how the timing constraints are applied.
Same goes for the UCF file, if you happen to use ISE.
Regards,
Eli