5GHz PCIe Link Speed on AC701 Demo

Questions and discussions about the Xillybus IP core and drivers

5GHz PCIe Link Speed on AC701 Demo

Postby mkarasoff »

Hi,

I am trying to get 5GHz PCIe link speed working on an AC701 Demo platform using Vivado. I have gotten the demo to work at 2.5GHz, but, when I change the PCIe core link speed to 5GHz, things go bad. The Linux host system I'm using for development does not recognize the PCIe card at boot - the card does not appear under lspci. If I switch the PCIe core link speed back to 2.5GHz, all is well. I believe the system should work at the higher link speed - Xilinx's AC701 TRD demo works on the system at 5GHz.

The only changes I'm making to the demo project is to the PCIe core link speed to 5GHz and re-entering Device ID to EBEB and user clock to 125MHz (for whatever reason the Device ID and user clock get reset when I change the speed). Do I need to make additional changes to the project to get 5GHz to work?

Thanks,
Mike
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Re: 5GHz PCIe Link Speed on AC701 Demo

Postby support »

Hello,

The reason it failed is most likely that changing the PCIe parameters may change the clock frequencies required by this Xilinx' PCIe block. In the (relatively old) revision on this block, which is used by the Xillybus bundle, this clock is generated by a module (pipe_clock) which the user logic has to instantiate and set up its parameters for. It's quite unfortunate, but that's the way it is.

The pipe_clock module is instantiated in xillybus.v, and a manual modification of the instantiation is required. The instantiation parameters PCIE_LINK_SPEED, PCIE_USERCLK1_FREQ and PCIE_USERCLK2_FREQ in particular may need an adjustment. If these aren't set correctly, odds are that the PCIe interface will not be detected at all by the computer.

The easiest way to get the correct parameters after making a change is to open a sample design of the PCIe block (in Vivado, right-click Xilinx' PCIe block's entry in the Sources view, and pick "Open IP Example Design...), and synthesize it. Then search for these names in the synthesis report, which states what those parameters should be set to. The example design should be created after changing the PCIe link parameters, of course.

It's also important to update xillydemo.xdc to reflect changes in the XDC file supplied by the example design. In fact, it might make sense to create one example design before the change, and one after, and compare them. Compare the XDC files with a diff utility, because the changes might be subtle, such as the "set_case_analysis" statements, which have a significant effect on how the timing constraints are applied.

Same goes for the UCF file, if you happen to use ISE.

Regards,
Eli
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Re: 5GHz PCIe Link Speed on AC701 Demo

Postby Guest »

Hi Eli,

Thanks for the pointers. Looks like I will have to slog through this.

Was the pipe_clock module something generated by the older PCIe block? Is there any documentation on what the number values for PCIE_LINK_SPEED, PCIE_USERCLK1_FREQ and PCIE_USERCLK2_FREQ represent?

MIke
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Re: 5GHz PCIe Link Speed on AC701 Demo

Postby support »

Hello,

The pipe_clock module is generated automatically in the example design, but with a rather tangled calculation of the parameters. So the easiest way is to grab the values from the synthesis report. As far as I know, there is no documentation on these parameters.

Regards,
Eli
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Re: 5GHz PCIe Link Speed on AC701 Demo

Postby mkarasoff »

Hi Eli,

Ok, working now. Looks like the AXI bus width changes to 128 bits if I keep the AXi clock at 125MHz. I expect the wider bus broke something. I set the clock to 250MHz and it now works.

250MHz may not be ideal for my app. I want a 1 lane configuration at 5GHz, and so prefer a 62.5 AXI clock to make timing easier. I will mess with the clock PCIE_LINK_SPEED, PCIE_USERCLK1_FREQ and PCIE_USERCLK2_FREQ and post if I can get working at the lower speed.

Thanks again for all your help.

Mike
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Re: 5GHz PCIe Link Speed on AC701 Demo

Postby support »

Hello,

Working at 250 MHz? Are you sure that you've adapted the timing constraints to the new setting? As far as I recall, Xillybus IP Core's own logic doesn't reach 250 MHz on AC701.

You might want to drop an email to Xillybus' support and ask for access to a revision XL demo bundle. It works with a 128 bit AXI interface, and might even be preconfigured with Gen2 PCIe.

Either way, the bus clock doesn't have to be related to the user application clock at all: If you replace the FIFOs in the demo bundle with dual-clock ("asynchronous") FIFOs, you may have any clock frequency for your application logic, and let Xillybus go on with whatever it's set to run with.

Regards,
Eli
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