Interface SPI hardware

Questions and discussions about the Xillybus IP core and drivers

Interface SPI hardware

Postby zer0c00l » Wed Aug 31, 2016 4:10 am

I have a Microzed board with Xillybus Linux running on it. I want to interface an ADC over SPI using the PMODs. How do I enable SPI on Xillybus?
I have tried opening the block design, double clicking on "processing_system7_0" and then enabling SPI 0 over EMIO. I have also made the SPI 0 external. Now How do I assign this to a PMOD, and then continue with generating a bitstream file?

Image
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Re: Interface SPI hardware

Postby support » Wed Aug 31, 2016 6:47 am

Hello,

Unfortunately, the Zynq device's hardware SPI interface isn't enabled in Xillinux-1.3 by default, so it's quite a way to go in order to make it work (change the setting in Xilinx' tools, recompile the FSBL and U-boot and then set up the device tree to work with it).

On the other hand, Linux has an SPI bit-banging feature, which is enabled in Xillinux' Linux kernel. You may assign any GPIO pins for your SPI bus, and just add an entry to the device tree. An /dev/spidevXXX device file will be created by the driver.

See http://lxr.free-electrons.com/source/Do ... txt?v=3.12
and http://xillybus.com/tutorials/device-tree-zynq-1

And this may come handy for getting the GPIO numbering right:

http://billauer.co.il/blog/2014/07/bash-gpio-xillinux/

The drawback of this method is that the CPU will be used for toggling the SPI pins. If you're not into heavy-duty communication on the SPI bus (or if you don't care about CPU consumptions while that's happening), this is definitely the easiest way to go.

Regards,
Eli
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Re: Interface SPI hardware

Postby zer0c00l » Wed Aug 31, 2016 6:25 pm

Thanks for the response.
If I somehow manage to edit FSBL, and U-Boot to enable the SPI will the same bitbang driver work for hardware spi or will it need a new driver?
If it needs a new driver is that available?
zer0c00l
 
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Re: Interface SPI hardware

Postby support » Wed Aug 31, 2016 7:11 pm

Hello,

For using hardware SPI, you'll need to set up a device tree entry that matches the driver for Zynq's SPI interface instead. That driver is part of Xillinux-1.3, so once you got the hardware module activated, it's just a matter of adding that device tree entry.

Regards,
Eli
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Re: Interface SPI hardware

Postby Guest » Wed Aug 31, 2016 8:09 pm

As far as activating the hardware goes, what I did was after running xillydemo-vivado.tcl script I tried enabling SPI 0 in processing_system7_0. After synthesizing and running Implementation I am unable to assign pins to SPI 0. If I open the I/O ports windows in Vivado it is empty even though I enabled SPI 0. If I just make a new design instead of modifying Xillydemo and enable SPI0 then I can see items in I/O ports windows like this

Image

This is what I see if I just modify the Xillybus design to enable SPI 0. Since it is empty how to I assign SPI to a particular PMOD?

Image
Guest
 

Re: Interface SPI hardware

Postby support » Fri Sep 02, 2016 1:43 pm

Hello,

This goes slightly beyond the scope of this forum. I suggest trying Xilinx' forum.

Regards,
Eli
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Re: Interface SPI hardware

Postby zer0c00l » Fri Sep 02, 2016 6:15 pm

So this has nothing to do with the way the xillybus design is setup in vivado?. This is what I was thinking, maybe adding hardware is disabled.
Thanks for clearing it up
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Re: Interface SPI hardware

Postby zer0c00l » Sun Sep 04, 2016 12:48 am

eli wrote:Hello,

This goes slightly beyond the scope of this forum. I suggest trying Xilinx' forum.

Regards,
Eli


I have managed to modify the design, and have added SPI. Now can the rebuilding of FSBL be done in Vivado, or would I need ISE?
zer0c00l
 
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Re: Interface SPI hardware

Postby support » Sun Sep 04, 2016 5:39 am

Hello,

Answered on this thread: viewtopic.php?f=4&t=456

Regards,
Eli
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