Questions related to Xillybus usage

Questions and discussions about the Xillybus IP core and drivers

Questions related to Xillybus usage

Postby Guest »

Hi Eli,

after using Xillybus for a while to communicate data between the PS and an accelerator in the PL in Zynq i want to try some more "exotic" setup and have some questions about it, so
1) If i setup Xillybus with 4 PS to PL interfaces with the same configuration(databus width, bandwidth etc.), how will Xillybus serve all interfaces if in my C code i send to each interface the same amount of data and call write() as shown below?
Code: Select all
/* sizeof(buffer_1) = sizeof(buffer_2) = sizeof(buffer_3) = sizeof(buffer_4) */
do something here
write(interface_1_fd, buffer_1, sizeof(buffer_1));
write(interface_2_fd, buffer_2, sizeof(buffer_2));
write(interface_3_fd, buffer_3, sizeof(buffer_3));
write(interface_4_fd, buffer_4, sizeof(buffer_4));
do something else here

2) Knowing Xillybus philosophy of one IP multiple interfaces, i want to experiment with multiple Xillybus instances. Can Xillybus device drivers handle multiple instances of Xillybus?
3) If it is possible to use multiple Xillybus cores and i connect them to the HP ports of Zynq, will this setup degrade its performance?

Thanks,
John
Guest
 

Re: Questions related to Xillybus usage

Postby support »

Hello.

(1) What happens on the write() call is that the data is written to a DMA buffer and the logic is informed that data is ready. The logic fetches the data by issuing bus cycles on the processor's bus. If there are several streams with data ready, the bus is accessed in a round-robin manner by the logic. Effectively, it will appear like all streams fetch data simultaneously.

(2) Yes, you may connect several instances of Xillybus, but that requires a different driver, which is usually requested for the PCIe variant of Xillybus.

(3) The answer is yes, but it won't probably make much sense. If you want multiple streams, set up a custom IP core to support that. The thing is that the Xillybus IP core is connected to the ACP port, in order to avoid the driver's need to synchronize the cache when accessing the DMA buffers. If Xillybus is connected to an HP port, cache synchronization is mandatory, which slows down the maximal data rate to 200 MB/s due to CPU consumption of the cache synchronization commands. So using the HP you'll end up with no CPU left for doing anything else, and a slower rate.

Regards,
Eli
support
 
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