Questions related to Xillybus usage
Posted:
Hi Eli,
after using Xillybus for a while to communicate data between the PS and an accelerator in the PL in Zynq i want to try some more "exotic" setup and have some questions about it, so
1) If i setup Xillybus with 4 PS to PL interfaces with the same configuration(databus width, bandwidth etc.), how will Xillybus serve all interfaces if in my C code i send to each interface the same amount of data and call write() as shown below?
2) Knowing Xillybus philosophy of one IP multiple interfaces, i want to experiment with multiple Xillybus instances. Can Xillybus device drivers handle multiple instances of Xillybus?
3) If it is possible to use multiple Xillybus cores and i connect them to the HP ports of Zynq, will this setup degrade its performance?
Thanks,
John
after using Xillybus for a while to communicate data between the PS and an accelerator in the PL in Zynq i want to try some more "exotic" setup and have some questions about it, so
1) If i setup Xillybus with 4 PS to PL interfaces with the same configuration(databus width, bandwidth etc.), how will Xillybus serve all interfaces if in my C code i send to each interface the same amount of data and call write() as shown below?
- Code: Select all
/* sizeof(buffer_1) = sizeof(buffer_2) = sizeof(buffer_3) = sizeof(buffer_4) */
do something here
write(interface_1_fd, buffer_1, sizeof(buffer_1));
write(interface_2_fd, buffer_2, sizeof(buffer_2));
write(interface_3_fd, buffer_3, sizeof(buffer_3));
write(interface_4_fd, buffer_4, sizeof(buffer_4));
do something else here
2) Knowing Xillybus philosophy of one IP multiple interfaces, i want to experiment with multiple Xillybus instances. Can Xillybus device drivers handle multiple instances of Xillybus?
3) If it is possible to use multiple Xillybus cores and i connect them to the HP ports of Zynq, will this setup degrade its performance?
Thanks,
John