xillybus with 3.5GB bandwidth interfacing HLS

Questions and discussions about the Xillybus IP core and drivers

xillybus with 3.5GB bandwidth interfacing HLS

Postby Guest »

Hi Eli,

Xillybus is an amazingly great tool, well debugged, well documented, well issued by automatic IP generation. I am wondering when the 3.5GB with direct HLS interfacing would be ready?

Maybe we can install several boards on one machine and do cluster computing with multiple such machines. HLS give us the flexibility to make any algorithm while Xillybus provide the infrastructure. That would be fantastic for scientific computing acceleration or other cloud computing applications.

Best,
Chongxi
Guest
 

Re: xillybus with 3.5GB bandwidth interfacing HLS

Postby support »

Hello,

Thanks for your encouraging words on Xillybus.

I suppose you refer to the AXI streaming interface, which makes it possible to connect HLS blocks using plain Vivado block design. This has been promised for the second half of 2016, and it seems like it's going to be rather late this year.

If you have plans on such a tool, please drop a mail. Maybe a preview kit can be organized.

Regards,
Eli
support
 
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Re: xillybus with 3.5GB bandwidth interfacing HLS

Postby sharpli »

Hi Eli,

Now is 2017. Could you please give us an update about what is the progress of the new version Xillybus?

I am excited to the whole project!

Thanks,
sharpli
 
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Re: xillybus with 3.5GB bandwidth interfacing HLS

Postby support »

Hello,

The AXI Stream bundle is already part of both the demo bundle and the cores generated by the IP core factory. These were indeed released in 2016, even though quite late...

As for the docs, there's something rather preliminary out published currently. The full document will be out in mid-January or so. You may request a preview version of it from Xillybus' support.

Regards,
Eli
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