The Xillybus Forum

Hi,

This might a silly question. What is the frequency of bus_clk from Xillybus instantiation?

Is that from sys_clk 100 MHz, or from userclk1 250 Mhz?

Thanks.

Hello,

It depends on the FPGA target. For Kintex 7 / Virtex 7 and the Ultrascales bus_clk runs at 250 MHz.

Regards,
Eli