Hi Eli and all,
I use Xillybus and Xilinx VC707. There are two streams; and it just a loopback at the moment. What I want to calculate is the throughput for each direction, both directions and total throughput if I put my design in the middle.
My first reference is from the Xillybus' page itself: http://xillybus.com/doc/bandwidth-guidelines. But I am not quite sure about this.
What I've done is putting a clock tick for write/read using clock() (in the <time.h> function). I use C code in Windows btw. And this code also involve writing to a disk (using malloc to store the reading and fwrite to write to a file).
I just want to make a clarification, are these the correct results of what I have obtained for a loopback (of each different filesize)?
filesize; write; read
--------; ------; -----;
1 MB; 60 MBps; 60 MBps
2 MB; 130 MBps; 130 MBps
4 MB; 260 MBps; 260 MBps
8 MB; 420 MBps; 530 MBps
16 MB; 430 MBps; 1000 MBps
33 MB; 380 MBps; 1100 MBps
55 MB; 380 MBps; 1200 MBps
130 MB; 340 MBps; 1270 MBps
214 MB; 304 MBps; 1250 MBps
439 MB; 215 MBps; 1250 MBps
Then, how do I get the throughput for both directions? Is that just taking the lowest throughput to represent the 'whole throughput' in the loopback?
For example, taking 130 MB, should the throughput for both direction is 340 MBps, or something else? If something else, could you give me a hint/reference to obtain these.
And finally, I will break these two FIFOs and connect them with my design, and let say my design produce a throughput of 400 MBps, how do I calculate the whole throughput for my system?
Because I got (for 130 MB filesize): 340 MBps + 400 MBps + 1270 MBps. So how do I calculate the whole throughput.
Thanks for your answer.
Xillybus is great.