Problem with read() in coprocessing

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Problem with read() in coprocessing

Postby Guest »

Hi,
first of all, you have done a very good job with xillybus and there is a lot of documentation to read from.

I'm using Zedboard and Xillinux/Xillybus to accelerate an operation. I've modified xillydemo.vhd to integrate my HW accelerator. I've broken the loopback of the demo, create another 32x512 FIFO using the same component in xillydemo.vhd and put my accelerator in between the two FIFOs. The host write on one FIFO and read from the other one. The accelerator read from the first and write the result to the second FIFO. I think this is the normal way of using Xillybus for coprocessing.

Vivado generates correctly the bitstream but the problem is on the execution of my system. When I try to read from the respective read file on the host, I have no result. I don't know how to fix this. I've read the documentation on Xillybus website and simulated my accelerator separately and it works. So, for sure, the problem is in my comprehension on how to integrate custom vhdl with xillybus.

I have another question : why vivado complains if I use as clock for my accelerator bus_clk?

I put here the xillydemo.vhd portmap of my setting :

Code: Select all
--  32-bit FIFO (host to fpga)

  fifo_32_hf : fifo_32x512
    port map(
      clk        => bus_clk,
      srst       => reset_32,
      din        => user_w_write_32_data,
      wr_en      => user_w_write_32_wren,
      rd_en      => rd_en,
      dout       => din_std,
      full       => user_w_write_32_full,
      empty      => empty_read
      );

  reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
 
  din <= unsigned(din_std);
 
--  ACCELERATOR

  acc0 : ACCELERATOR
    port map(
      clk        => clk,
      srst       => reset_32,
     empty_read => empty_read,
     full_write => full_write,
      din        => din,
      dout       => dout,
      rd_en       => rd_en,
      wr_en      => wr_en
      );
 
   process
     begin
        clk <= '0';
        wait for 5 ns;
        clk <= '1';
        wait for 5 ns;
   end process;
 
--  32-bit FIFO (fpga to host)

  fifo_32_fh : fifo_32x512
    port map(
      clk        => bus_clk,
      srst       => reset_32,
      din        => dout_std,
      wr_en      => wr_en,
      rd_en      => user_r_read_32_rden,
      dout       => user_r_read_32_data,
      full       => full_write,
      empty      => user_r_read_32_empty
      );

  dout_std <= std_logic_vector(dout);    
    
  user_r_read_32_eof <= '0';


Thanks for your help!
Guest
 

Re: Problem with read() in coprocessing

Postby support »

Hello,

What complaint did Vivado have if you use bus_clk to run your logic? It should be perfectly fine.

Regarding the clocking in general: You have instantiated two single-clock FIFOs. As such, all data and control signals going to these FIFOs must be clocked with bus_clk. If you want to stick to your own clock, generate and instantiate a dual-clock ("asynchronous") FIFO instead. Then you can clock each side of the FIFO with a different clock, and it's perfectly fine.

Now to the generation of clk with a VHDL process: That works in a simulation, but as far as I understand, clk will not toggle in a real-life design. There just isn't a clock generator in an FPGA. You must supply an external clock, or use some PLL/MCMM to generate one clock from another.

So odds are that the synthesizer assigned a constant clk=0, and then eliminated all logic in the accelerator logic by virtue of optimization of logic that will never toggle. That explains why you saw nothing on the output.

Regards,
Eli
support
 
Posts: 802
Joined:

Re: Problem with read() in coprocessing

Postby Guest »

Thank you for the reply!

If I use bus_clk instead of clk in the port map of my accelerator, the implementation phase in the "Generate Bitstream" fails and this is the error message :

Code: Select all
[showstopper 1] There are registers with no clock. Please check your design. See Timing Summary Report.
[runtcl 1] ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
Guest
 

Re: Problem with read() in coprocessing

Postby support »

Hello,

This is the showstopper.tcl scripts telling you that there's a serious error in the timing report. In your case, there are registers with a clock that doesn't toggle.

Could it be that you've used the clock generated in VHDL for some purpose in the design? Or maybe done some other manipulation with clocks?

Regards,
Eli
support
 
Posts: 802
Joined:

Re: Problem with read() in coprocessing

Postby Guest »

In my accelerator I have one state machine and one adder. The process for the regs of the state machine is this one :

Code: Select all
FSM_REG : process (clk)
      begin
        if (clk'event and clk = '1') then
         if srst = '1' then
               CURRENT_STATE <= WAIT_READ_FIFO;
         else
               CURRENT_STATE <= NEXT_STATE;
         end if;
        end if;
    end process FSM_REG;


The process of the adder is this one :

Code: Select all
process (clk)
      begin
      if (clk'event and clk = '1') then
         if (srst = '1') then
           dout <= "00000000000000000000000000000000";   
           done <= '0';       
         elsif (go = '1') then
           dout <= din + "1";   
           done <= '1';
         else
           done <= '0';      
         end if;
      end if;
    end process;


I don't know where is the problem beacause this seems to be correct.
Guest
 

Re: Problem with read() in coprocessing

Postby support »

Hello,

I can see nothing immediately alarming in the code you've posted, but there are missing pieces. Why is there a state machine? I can't see how CURRENT_STATE is used etc.

But never mind. This forum is for Xillybus support, and the discussion has moved to general VHDL coding practices. I suggest getting help at one of Zedboard's or Xilinx' forums.

Regards,
Eli
support
 
Posts: 802
Joined:

Re: Problem with read() in coprocessing

Postby Guest »

Ok. Thank you for the help!
Guest
 


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