minimal configuration

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minimal configuration

Postby Guest »

Hello,

I am sorry for my beginner question. I am new in the FPGA world - but I would like to know what is the minimal configuration for the custom IP.

I have generated the custom Xillybus IP. Now I want to add it to the Zynq-based design in Vivado. I need only to stream data from the PS to PL, nothing more.
One stream is enough for me. I am not sure what else (what IP cores) I have to add to the design to make one stream from the PS to PL work.

I tried to look at the Xillybus reference design but it seems that there is much more that I need and I get confused from this complex design.

Can someone write me the steps needed to implement the Xillybus custom IP to the Zynq design, please?

For the moment, I have made the following steps:

1) Generated Xillybus custom IP and download it
2) Created a new Vivado project (VHDL)
3) Created design and set Zynq processing system parameters for my board
4) Added the custom Xillybus IP Core to the design and run connection automation
5) What else? I do not know what I have to add and what to do further...Add a FIFO? If yes, is there some FIFO IP Core working with Xillybus or I have to write some in VHDL? The IP Core has still the following ports unconnected:
- to_host_fpgahost
- ap_clk
- bus_rst_n
- m_axi
- from_host-write_32
- GPIO_LED[3:0]
- host_interrupt
- quiesce
- to_host_fpgahost_open
- from_host_write_32_open

Thank you in advance for every advices.

Jirka
Guest
 

Re: minimal configuration

Postby support »

Hello,

I suggest building Xillinux for your target. That indeed gives you more than you need, but you can ignore all of it, and focus on the xillydemo.v/.vhd file. That gives you a quick start, and a working kit that you can make changes in Verilog/VHDL without getting into too much details.

The Getting Started guide for Zynq targets explains the flow.

If you want to work with a custom IP core, the README file tells you what to do. But I suggest getting acquainted with the demo bundle first.

Trying to get it working from scratch is the much longer path to go.

Regards,
Eli
support
 
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Re: minimal configuration

Postby Guest »

Hello,

thank you for your fast reply!

But...

There is more aspects I have to consider. At first, a purpose of the minimal design I spoke about in my first message is only to get familiar with Xillybus. We have already more sophisticated one to which we finally need to implement Xillybus. At second, we already have the Linux (Linaro) built for our custom board. We have spent already more than 4 months to get working and tune everything we need for our project. So, that is why we need to implement Xillybus to our project - not contrary. Moreover, there will be much more work than half an hour (if I reference the Xillybus manual) with the custom board we have. It is not one of your referenced ones. :-)

So, please, can you provide any other suggestions to help me implement Xillybus to our design?

Thank you a lot, greetings,

Jirka
Guest
 

Re: minimal configuration

Postby support »

Hello,

It still goes back to Xillinux, unfortunately. If you have one of the supported boards, it will help for trying it out, but either way, the best way is to use the Xillinux bundle as a reference. In particular, you'd like to see how Xillybus is hooked up to the system (via the ACP port) and how the various processor parameters are set.

So the task you have ahead is to mix and match between Xillinux and your own project: The processor's wiring and configuration, updating the FSBL, and adding an entry into the device tree. And you might also need to enable Xillybus' device driver on the Linux kernel (and possibly patch it with this, if you're in the range of affected kernels):

https://patchwork.kernel.org/patch/8402871/

Regards,
Eli
support
 
Posts: 802
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