Accessing JA PMOD with programmable logic

Questions and discussions about the Xillybus IP core and drivers

Accessing JA PMOD with programmable logic

Postby kresica » Thu Jun 08, 2017 2:57 pm

Hello,

I am using Xillybus for Zedboard. I am trying to implement serial TX/RX communication for which I would like to use JA PMOD connector on ZedBoard. Unfortunately for me, JA PMOD is already used as an EMIO GPIO in Zynq PS, so I decided to edit Zynq PS IP core to use only 54 EMIO GPIO ports (instead of default 56).
I have edited system.v and xillybus.v sources (from upper hierarchy) to accommodate vector of size 54 instead of 56 and I have edited constraints in which I removed PS_GPIO[54] and PS_GPIO[55] pin location declarations.

I decided to assign my RX to Y11 location, which was assigned to PS_GPIO[24], and my TX to AA11 location, which was assigned to PS_GPIO[25].
I assigned U6 and U5 locations to PS_GPIO[24] and [25], which were assigned to now removed signals PS_GPIO[54] and [55].

I get critical warnings during synthesis saying "Cannot set LOC property of ports, loc is blocked" which points to my TX and RX signal declarations in XDC file.
Synthesis and implementation design runs complete successfully but bitstream generation fails due to "unconstrained ports" (UCIO-1).

I'm running in circles trying to resolve this problem, I've tried using I/O planning and fixing ports which assignes my TX and RX signals to FMC which is unacceptable. Please help.

Best regards,
kresica
kresica
 
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Re: Accessing JA PMOD with programmable logic

Postby support » Thu Jun 08, 2017 3:22 pm

Hello,

Have you looked at section 5.4 of the Getting Started Guide?

http://xillybus.com/downloads/doc/xilly ... d_zynq.pdf

It's written in terms of ISE (with UCF constraints) but it's in principle the same with XCF.

Regards,
Eli
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Joined: Tue Apr 24, 2012 3:46 pm

Re: Accessing JA PMOD with programmable logic

Postby kresica » Thu Jun 08, 2017 3:27 pm

I suppose I suffer from a case of RTFM :)
Will try the solution described in guide, thanks a bunch.

Best regards,
kresica
kresica
 
Posts: 7
Joined: Fri Nov 18, 2016 6:20 pm

Re: Accessing JA PMOD with programmable logic

Postby kresica » Thu Jun 08, 2017 8:54 pm

Just a quick follow-up if someone sometimes encounters the same problem as me.

As I reviewed the user guide, I realized I have done the very same thing as described in guide but problem persisted. After a couple of very frustrating hours and mindless guessing where is the problem, I finally found the root cause.

First a little background story - I am implementing TX/RX with ISERDES/OSERDES primitives which use ILOGIC and OLOGIC cells. Upon opening Window -> Package Pins in Implementation flow, I've noticed I can't map TX/RX ports to no pins from Bank 13 where JA, JB, JC and JD PMODs reside. That baffled me since I saw in Device view that pins for PMOD have ILOGIC and OLOGIC cells nearby and according to datasheet (UG471), all IO banks were of same type (HR) for ZedBoard and were capable to use SERDES.

In one of a many random tries I decided to remove all EMIO GPIOs for PMODs and that finally worked! Although it is behind my knowledge why. Now I'm happy and I can move on to other problems that await, woooo!!

Best regards,
kresica
kresica
 
Posts: 7
Joined: Fri Nov 18, 2016 6:20 pm


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