Does Xillybus support the Kintex UltraScale FPGA KCU1500?

Questions and discussions about the Xillybus IP core and drivers

Does Xillybus support the Kintex UltraScale FPGA KCU1500?

Postby Guest »

I have the Kintex UltraScale FPGA KCU1500 Acceleration Development Kit. There is no demo bundle for it on the site. Does Xillybus support the board?

Re: Does Xillybus support the Kintex UltraScale FPGA KCU1500

Postby support »


Xillybus supports all Kintex Ultrascale FPGAs (and others as well, of course). To make the it work on your board, please download the demo bundle for KCU105 at the website, unzip the bundle and modify it as follows:

In vivado-essentials/main.tcl, change the line 4 to reflect the FPGA part in use. For example, for board with the early evaluation sample FPGA, it will say

Code: Select all
set thepart "xcku115-flvb2104-2-e"

Also replace vivado-essentials/xillydemo.xdc with the following:
Code: Select all
create_clock -name sys_clk -period 10 [get_ports PCIE_REFCLK_P]

set_clock_groups -name async1 -asynchronous \
  -group [get_clocks -include_generated_clocks -of_objects [get_ports PCIE_REFCLK_P]] \
  -group [get_clocks -include_generated_clocks -of_objects [get_pins [all_fanin -flat -startpoints_only [get_pins -hier -filter {name=~*/gt_top_i/phy_clk_i/CLK_USERCLK_IN}]]]]

set_false_path -from [get_ports PCIE_PERST_B_LS]

set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports PCIE_PERST_B_LS]

set_property LOC AT11 [get_ports PCIE_REFCLK_P]

set_property -dict "IOSTANDARD LVCMOS18 PULLUP true" [get_ports PCIE_PERST_B_LS]

set_property -dict "PACKAGE_PIN AW25 IOSTANDARD LVCMOS18" [get_ports "GPIO_LED[0]"]
set_property -dict "PACKAGE_PIN AY25 IOSTANDARD LVCMOS18" [get_ports "GPIO_LED[1]"]
set_property -dict "PACKAGE_PIN BA27 IOSTANDARD LVCMOS18" [get_ports "GPIO_LED[2]"]
set_property -dict "PACKAGE_PIN BA28 IOSTANDARD LVCMOS18" [get_ports "GPIO_LED[3]"]

The following changes in vivado-essentials/pcie_ku/pcie_ku.xci are also required when using recent Vivado revisions (starting from 2017.* or something like that):
Code: Select all
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">KCU105</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>

-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">0</spirit:configurableElementValue>

-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku040</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku115</spirit:configurableElementValue>

-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffva1156</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">flvb2104</spirit:configurableElementValue>

(the line with "-" should be replaced with the one with the "+")

Then build the demo bundle as usual (that is, follow "Getting started with the FPGA demo bundle for Xilinx").

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