stream read not behave as expected

Questions and discussions about the Xillybus IP core and drivers

stream read not behave as expected

Postby Guest » Sat Jul 29, 2017 5:02 pm


I am using stream read and write to tranfer files from host PC, process in the FPGA and send the data back.
In my project, an ILA is used to monitor the control signals from host pc to my fpga. However, sometimes the user_rd_en never raise even there is data in the read fifo of PC. And I also see user_rd_open keeps high even after I close the device file from the terminal. What could be the reason for this problem?

I wonder how the user_rd_en and user_wr_en generated? And is there any method in the host pc program that we can directly control these signals?

Greatly appreciate for any help in advance!


Re: stream read not behave as expected

Postby support » Sat Jul 29, 2017 6:33 pm


It's not clear which signals you're referring to. And in case you user_rd_en refers to e.g. user_r_read_32_rden, what do you mean that the signal is never raised? Is there data in the FIFO which is never read? I find that quite unlikely, as it would have been a blunt bug that couldn't have gone unnoticed after so much mileage.

Please clarify what you've done, and what seems to be wrong.

Posts: 482
Joined: Tue Apr 24, 2012 3:46 pm

Return to Xillybus