Timing constraints for an asynchronous design

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Timing constraints for an asynchronous design

Postby Guest » Sat Jul 29, 2017 5:27 pm

Hi,

I am using an independent clock FIFO with the write clock being 250MHz and read clock as 125MHz. The write clock is the bus_clk which is the same as given in demo project. I am using a PLL to generate the read clock of 125MHz. In order to consider the two clocks as asynchronous, I am not sure how to set the constraints in Vivado. Which clock should be used as source for 250MHz clock? Is it the bus_clk or the user_clk1 from which bus_clk actually comes from? Can anyone provide me some suggestions.



Thanks
Guest
 

Re: Timing constraints for an asynchronous design

Postby support » Sat Jul 29, 2017 6:45 pm

Hello,

This isn't really a question on Xillybus, but rather on general timing constraining. So I suggest referring to Xilinx' documentation and forums.

Anyhow, take a look on the timing report. I believe that you'll find that the 125 MHz is already constrained, as it's derived from the 250 MHz clock by a PLL. The tools usually automatically add a timing constraint in that case.

Then you might need to declare that the two clocks should be treated as unrelated ("asynchronous"). There is a special timing constraint for that (set_clock_groups -asynchronous). But in your special case of a 1:2 ratio, it might not make a big difference. In particular, if the PLL is set to align its output (125 MHz) with the input clock (250 MHz), the paths between these two clock domains won't cause any trouble, even in the absence of a set_clock_groups constraint. And it's safer that way (in case you accidentally generate some logic that crosses clock domains without due protection).

Regards,
Eli
support
 
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