Disable JTAG in Xillinux?

Questions and discussions about the Xillybus IP core and drivers

Disable JTAG in Xillinux?

Postby gutielo » Fri Aug 18, 2017 8:56 pm

Hello. I'm using the XADC and writing the converted values to a FIFO, then read the FIFO to get those values. It happens to work good until the FIFO gets filled for the first time (FULL is asserted). After that, all the values being written to the FIFO (that is, after reading the FIFO thus emptying its initial content) make no sense since they're being read from channel 9, which happens to be an invalid channel (as stated in UG480). I'd like to see if JTAG has something to do with this since I checked JTAGLOCKED from XADC and was asserted high once and maybe it's changing some of the config regs of the XADC. In an attempt to disable JTAG, I added this to the constraints file:

set_property BITSTREAM.GENERAL.JTAG_XADC Disable [current_design]

But JTAGLOCKED kept being asserted, so it looks like it wasn't very useful.

So I was wondering how can I disable JTAG in Xillinux? I was wondering if it would be enough to decompile the device tree file in my SD card, delete the XADC entry, compile it again and try to run Xillinux with that. Would that be enough or it has nothing to do with that? If not, how could I achieve this?

Or maybe you think the problem might be something different given the description I gave?
gutielo
 
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Joined: Sun Jul 23, 2017 4:17 pm

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