Fifo eof

Questions and discussions about the Xillybus IP core and drivers

Fifo eof

Postby JohnT » Wed Aug 30, 2017 7:10 pm

Hi All,

We implemented an FIFO to access the SPI on the FPGA, the communication works okay except some behavior that I am getting. Below are the pseudo commands on how I communicate to the SPI.

1. open the device (xillybus_spi)
2. write spi commands
3. read the data

#For some reason, the pipe has some left over data, so I added the command below to empty the pipe.
4. read data until I get the EOF before proceeding to step 5.

5. close the device.


The behavior that I was having is that doing the #4 and for unknown reason (the pipe is empty), the read function never return and never received the EOF signal.

My questions:
1. Is there a way that every time my program open or close the device, the driver (xillibus) will throw away the left over data?
2. Does the FPGA able to detect if the device has been opened or closed then send a signal to the xillybus driver to throw away the left over data?.
3. If the pipe is empty, is there any kind of configuration setting that we can add in FPGA that if the pipe is empty, send EOF?.

Regards,

John
JohnT
 
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Re: Fifo eof

Postby support » Wed Aug 30, 2017 8:31 pm

Hello,
JohnT wrote:1. Is there a way that every time my program open or close the device, the driver (xillibus) will throw away the left over data?

This is what the driver actually does. But data may have been left in the FIFO, in particular if the stream towards the host is synchronous. To get rid of this data, simply connect the FIFO's reset port to the inverse of the respective stream's *_open signal, and it will be emptied when the file is closed.

Synchronous vs. Asynchronous streams are discussed in section 2 of the host application programming guides, e.g.
http://xillybus.com/downloads/doc/xilly ... _linux.pdf

JohnT wrote:2. Does the FPGA able to detect if the device has been opened or closed then send a signal to the xillybus driver to throw away the left over data?.

Yes, this is what the *_open signal is for. Please refer to Xillybus FPGA designer’s guide, section 3.3:
http://xillybus.com/downloads/doc/xillybus_fpga_api.pdf

JohnT wrote:3. If the pipe is empty, is there any kind of configuration setting that we can add in FPGA that if the pipe is empty, send EOF?.

Yes, this is what the *_eof is signal does, also described in section 3.3 mentioned above.

Regards,
Eli
support
 
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