Read() call not returning, yet FIFO being read

Questions and discussions about the Xillybus IP core and drivers

Read() call not returning, yet FIFO being read

Postby mkarasoff » Fri Sep 22, 2017 7:22 pm

I'm having some trouble with a streaming interface that I've set up for a short message passing application. The interface is a byte wide Xillybus stream, connected to a FIFO in the FPGA. The messages which are failing are quite short, 2 or 3 bytes. I've tried this with both synchronous and asynchronous core options.

About 50% of the time, the read() call to the interface does not return; however, I've instrumented the FIFO interface with chipscope (or whatever the Vivado version is called) and confirmed that the FIFO is being completely read to empty on every access, regardless of whether or not read() returns. What is quite curious is that, even if the read call only requests one byte, all 2-3 bytes will be read from the FIFO. Is this expected behaviour for both synchronous and asynchronous access? Does the short message size explain why read hangs? Are there any options for the core that may fix this?
mkarasoff
 
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Re: Read() call not returning, yet FIFO being read

Postby mkarasoff » Sat Sep 23, 2017 12:06 am

An update: Changing the the Xillybus stream interface from 8 to 32 bit width, writing a byte into the 32 bit word, e.g.
Code: Select all
{24'h000000, byte}
, seems to work. Now a read() call for 1 byte no longer hangs. Can someone confirm if this is expected behaviour? Do I have a workaround for a bug, or is flakiness on byte wide accesses an expectation I should have?
mkarasoff
 
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Re: Read() call not returning, yet FIFO being read

Postby support » Sat Sep 23, 2017 6:00 am

Hello,

Since the Xillybus IP core and its driver has quite a mileage, I can say with confidence that there is no bug causing the behavior you describe. There's no chance such ridiculous misbehavior would have gone unnoticed.

If you happen to use Linux with the driver in the kernel (between 3.18 and 4.6), I suggest trying the one available for download at the website, as there was a slight bug in this range. Even though I doubt this would cause what you describe.

To put it short: Data that is written to the FIFO on the FPGA side will arrive at the host. The read() will not block if there's data available. If this happens to you, I suggest looking for:

(1) That timing constraints are met on the FPGA side
(2) No bug in the application software (has the data already been consumed?)
(3) Other really bad things happening (PCIe card yanked out of place etc.)

Regards,
Eli
support
 
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