Some questions after reading doc of the guide to Xillybus li

Questions and discussions about the Xillybus IP core and drivers

Some questions after reading doc of the guide to Xillybus li

Postby Guest »

Hi, dear elites,

I got some questions after reading the doc. Please feel free to comment. Thanks

Q: In the doc, it mentioned the maximal data rate is around
28 MB/s (7M 32-bit reads or write accesses per second, with the processor clock at 666 MHz). What can user understand the 7M here ? Is it the fastest clocking speed of the Xilinux lite IP ?

Q: In the doc of the guide to Xillybus lite, it uses the following example :
# ./uiotest /dev/uio0 4096
0 1 2 3

what's the meaning of 4096 in the test code here ?

Q: Would you please illustrate when user can use more than one Xillybus Lite instance ?

Q: What's the special meaning of lite in Xillybus lite ?

Thanks
NS
Guest
 

Re: Some questions after reading doc of the guide to Xillybu

Postby support »

Hello,

A: "7M" simply means 7 million. 7 million accesses of 32 bit (= 4 bytes) is simply 4 x 7 = 28 MB/s. That's all.

A: The number 4096 is the size of the region to mmap. It should match (actually, not be larger than) the allocated section allocated by the hardware peripheral.

A: It might be desired to attach more than one than one Xillybus Lite unit on the FPGA side. In that case, another device tree entry is made for it, which causes Linux to generate another /dev/uioN file (i.e. /dev/uio1).

A: "Lite" means that this isn't the fullblown Xillybus IP core, which is DMA based, much faster and can work over a PCIe bus as well. Xillybus Lite is lightweight, slow and relatively CPU demanding when used heavily, and is intended primarily for setting registers of hardware etc.

Regards,
Eli
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Re: Some questions after reading doc of the guide to Xillybu

Postby Guest »

Hi, Eli,

Thanks for the explanation.

Regarding to the number 4096, is the unit word (32-bit or word) or byte ?

Also, if user uses the xillybus demo bundle kit with Xillybus lite IP and also creates another AXI CDMA added in the PL, can the AXI CDMA access the Xillybus lite IP ? Or can the DMA in the PS access the xillybus lite IP module if user enables the DMA of PS to write date into the xillybus lite IP ? Thanks

All the best,
NS
Guest
 

Re: Some questions after reading doc of the guide to Xillybu

Postby support »

Hello,

The 4096 figure refers to bytes.

I suppose that the CDMA module can access Xillybus Lite's registers, but it's not a usage scenario that was intended, so it's not clear if this will work, neither why you want to do that. If you look for a DMA solution, the non-lite Xillybus IP core is intended for that.

Regards,
Eli
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Re: Some questions after reading doc of the guide to Xillybu

Postby Guest »

Hi,

Thanks for the comment.

Since I'm not familiar with non-lite Xillybus IP, I'm thinking of use of AXI DMA for the data movement part.

According to your suggestion, it seems to me that user can use one Xillybus lite IP for register configuration and one Xillybus IP for AXI master in terms of DMA access for the co-processor module under design. Thus, it turns out to have one AXI slave and one AXI master interface wrapped up by both non-lite and lite Xillybus IPs.

Is my understanding correct ? Is there any available example code for reference ?

All the best,
NS
Guest
 

Re: Some questions after reading doc of the guide to Xillybu

Postby support »

Hello,

Xillybus IP works standalone. There is no need to configure any of its registers or deal with any of the DMA tasks. It's a complete solution for transporting data. Hence no need to play around with Xillybus Lite, if you've got (non-lite) Xillybus in action.

Regards,
Eli
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