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One thread to write & one thread to read from Xillybus-lite

PostPosted:
by Guest
Hi,

Now we plan to use Xillybus Lite IP to integrate the FFT module with the following items :
- Implement one FIFO (or DP ram) to interface to the write interface of Xillybus-Lite IP i.e. user_wdata etc.
- Implement separate FIFO (or DP ram) to interface to the read interface of Xillybus-Lite IP i.e. user_rdata etc.

For SW implementation, we come up with the following questions for your comment.
Q1: The control SW program you suggest is to use Linux UIO as we find at your website. For Xillybus-Lite based design, is it possible to implement multi-threading code which one thread for writing data and the other thread for reading data only for highest performance ? We are wondering of both processes will access the same UIO ?

Q2: If yes, would you please show the associated reference code ?


Thanks in advance

Re: One thread to write & one thread to read from Xillybus-l

PostPosted:
by support
Hello,

Xillybus Lite implements a standard Linux UIO interface for a memory-mapped peripheral on the PL. There is no difference between this and any other Linux UIO device.

Accordingly, please refer to Linux resources on best practices for accessing UIO from a multi-threaded program. Not that I see why this would be an issue.

Regards,
Eli

Re: One thread to write & one thread to read from Xillybus-l

PostPosted:
by Guest
Thanks for the prompt reply. Since we're pure VLSI guys, we will look for help from SW people. Thanks