implement FIFO pointer R/W behavior over Xillybus Lite

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implement FIFO pointer R/W behavior over Xillybus Lite

Postby Guest » Tue Jan 23, 2018 8:00 pm

Hi, dear support,

We use the Xillybus lite in demo bundle for register access and it works in Zybo. However, due to have a 32 bits wide with 1K depth register file added, we utilize a register address as FIFO pointer to interface to a BRAM with 32 by 1024 bit.
But we encountered a issue, for example, write A5A5A5A5 and 5A5A5A5A in sequence to the BRAM via the FIFO pointer address over Xillybus lite and get A5A5A500, 5A5A5AA5, A5A5A55A, etc. It seems that bit 7:0 is delayed by 1T. Thus, I have the following questions.

I am not sure if we can implement FIFO pointer r/w over Xillybus lite in demo bundle. Another question is can the Xillybus lite of demo bundle 2.0a support 8kB memory map or only 4kB.

Finally, does it related to cache setting since the test code only write the same address for 1024 times and then read the same address for 1024 times ? The BRAM will be access by other ip with random read access and then we cannot use the Xillybus bus ip FIFO.


All the best,
thanks
Guest
 

Re: implement FIFO pointer R/W behavior over Xillybus Lite

Postby support » Tue Jan 23, 2018 8:16 pm

Hello,

Please refer to the documentation regarding the waveforms on the FPGA side as a result of write operations on the host:

http://xillybus.com/downloads/doc/xillybus_lite.pdf

The fact that you have a single byte off-beat is somewhat weird. Please make sure that you're writing 32-bit words to 32-bit aligned addresses. Alternatively, write single bytes and take account of the writing strobes. Whichever works best with your application logic.

As for expanding the address space: Yes, you may expand it to any size by changing the address map in Vivado's block design, and update Xillybus LIte's entry in the device tree accordingly.

I should mention in this context that non-Lite Xillybus is the natural solution for transporting data streams. It's available in Xillinux out of the box as well.

Regards,
Eli
support
 
Posts: 617
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Re: implement FIFO pointer R/W behavior over Xillybus Lite

Postby Guest » Tue Jan 23, 2018 9:27 pm

Hello,

Thanks for your comment.

Yes, for Xillybus lite, we did implement byte write decoding logic to collect the complete 32-bits word data after some FPGA debug.

For expanding the address space, we use 2.0a bundle design. Would you please elaborate how to update Xillybus LIte's entry in the device tree accordingly which we never do that ? Any reference is preferred.

Also, is it ok to continuous read or write the same address for tens/hundreds times w/o optimization since I suspected if it's cache issue or test code optimization ?

Thanks
Guest
 

Re: implement FIFO pointer R/W behavior over Xillybus Lite

Postby support » Tue Jan 23, 2018 10:10 pm

Hello,

If you implemented it with byte granularity, there's a chance the problem is in the application logic that handles the incoming data. I would suggest trying the same with 32-bit words, if that suits your application -- it's also 4 times faster.

References on the Device tree: Google would have helped here. There's one tutorial on this site:

http://xillybus.com/tutorials/device-tree-zynq-1

and also consider this section on the device tree on Xillinux-2.0:

http://xillybus.com/doc/xillinux-2.0

As for your last question: Xillybus Lite is based upon LInux' UIO, which is intended for direct memory access. So it works, no matter how often you access the mapped memory space. Besides, the underlying physical memory space is in the I/O region, and is hence not cacheable to begin with.

I suppose you are aware that the pointer used to access the hardware must be of volatile type...? Or the compiler can mess things up.

Regards,
Eli
support
 
Posts: 617
Joined: Tue Apr 24, 2012 3:46 pm

Re: implement FIFO pointer R/W behavior over Xillybus Lite

Postby Guest » Wed Jan 24, 2018 2:56 pm

Hi,

Thanks for your time to share with your valuable comment.

Yup. We did implement the logic you mentioned to receive the word data since we observed that CPU issues byte write address via xillybus lite which we cannot receive the whole word in one cycle.

After many debugging attempts, I finally have a summary about the issue. If we bring the same internal signals of BRAM output to another non-fifo pointer style register address and CPU can read back the correct date. However, if CPU read the data via the FIFO pointer address, it has data corruption in bit[7:0] which lost the bit 7:0 and put into next read data in bit 7:0. Thus, from our experiment, it seems that it has suspicious issue in FIFO pointer read operation via Xillybus Lite but FIFO pointer write operation works via Xillybus Lite. We implement the one 32-bit register address for both FIFO pointer read operation & FIFO pointer write operation. The test code is writtern by Python via UIO you suggested.

Since it takes time and I also don't know how to debug further in ZYBO, I just keep the status posted in the thread. Thanks
Guest
 


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