Hello,
I have implemented a Verilog module as a two-state FSM, with number of them coupled in a pipeline to perform computation.
The first stage is pre-loading 2 bit data values into each of the modules, second stage is streaming another load of 2 bit values across the initialized coupled modules.
I am wondering - what is the right way to make use of Xillybus IP and FIFOs to achieve such a goal?
I had a look into the manuals as well as the top-level xillydemo.v module, but I am getting confused with all the information presented.
All I need is to pre-load data (host-FPGA) to my modules, stream some data (host-FPGA) and stream the results back as they arrive (FPGA-host).
I would appreciate any pointers to where I can start. I know how FIFOs and shift registers operate, but I seem to not be able to put the whole picture together in my head.
Please indicate if I should elaborate more.
Thank you.