Xilinux Demo Bundle with DMA capability

Questions and discussions about the Xillybus IP core and drivers

Xilinux Demo Bundle with DMA capability

Postby Guest » Fri Feb 23, 2018 10:51 pm

Hi, dear support,

We're evaluating to utilize the Xilinux Demo Bundle as a base line for project use. However, in the requirement of the task, it requires to output data to DRAM. As we investigated, if we designed our IPs with either xillybus-lite or xillybus IPs, it still needs to output the data generated by the module to DRAM directly to offload loading of CPU. Thus, as you know, is it easier for user to hook up AXI master or AXI DMA for transportation to DRAM over Xilinux Demo Bundle ? Thanks
Guest
 

Re: Xilinux Demo Bundle with DMA capability

Postby support » Sat Feb 24, 2018 3:41 am

Hello,

The mainline Xillybus IP core, which is included in the Xillinux kit, is 100% DMA based. All data transport takes place by reading and writing to the PL's RAM through one of its AXI master port. So for the purpose of efficient DMA-based data transport, it can be used as is.

Regards,
Eli
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Re: Xilinux Demo Bundle with DMA capability

Postby Guest » Sat Feb 24, 2018 9:20 am

Hello,

Thanks for the clarification. It seems that I miss the DMA capability of Xillybus IP you mentioned. I just did a quick check on the website and whether I should refer to the following document for the part of DMA.

The use case of mine is to
- Block module generates data
- It needs a DMA master to move the data to DRAM in ZYBO w/o the involvement of CM9 CPU in ZYBO
- Then, CM9 CPU can begin to read the data in DRAM for further use

Thus, if there are other documentations including either HW or SW example I can leverage, please kindly share with me for further study. Thanks

http://xillybus.com/downloads/doc/xilly ... tom_ip.pdf
Guest
 

Re: Xilinux Demo Bundle with DMA capability

Postby support » Sat Feb 24, 2018 12:58 pm

Hello,

The Getting Started guide for Linux' chapter 3 shows a simple interaction with the logic to begin with:

http://xillybus.com/downloads/doc/xilly ... _linux.pdf

By modifying the logic design, you can insert your own data instead of the loopback.

Note however that Xillybus is an end-to-end solution, and does a bit more than you describe: The data is indeed transported to the processor's RAM, but the access to the data is done with file I/O.

Regards,
Eli
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