How do I make device look like standard serial port

Questions and discussions about the Xillybus IP core and drivers

How do I make device look like standard serial port

Postby helmutforren » Thu Apr 26, 2018 5:37 pm

I'll be using RHEL 7.4. My FPGA will have a serial port. That Tx/Rx data will go through Xillybus and appear as two named pipes on linux. How do I then make that look like a standard serial port, where one can use stty or setserial to configure it, and then write/read it?

Is there an easy way to do this?

Otherwise, below is text I posted at LinuxQuestions.org:




Under RHEL 7.4, I'm going to have some custom hardware and linux driver (Xilinx FPGA, Xillybus) that presents two named pipes, one Rx coming into the linux computer and one Tx going out. I would like to make that APPEAR to linux to be a standard serial port.

So I think I need a driver that gives the APPEARANCE of there being a standard serial port, that can be written or read from, and that can be configured via stty or setserial. I haven't gotten deep enough into this yet, and I'm hoping there will be easier ways to accomplish this, including just using existing programs or commands.

My lay understanding of what to do follows. Please correct or improve it for me! The best would be if I don't have to write any code at all. (I have written at least half a million of lines of code in the past. (I multiplied 20Klines by 40years to get 800K.))

For the Tx/Rx, I imagine that I would find some existing serial port driver code. The "top" layer would expose what looks like a regular serial port that can be written/read as well as configured via stty or setserial. I would then replace the "bottom" layer with writes to the Tx named pipe and reads from the Rx named pipe. For the control stuff, such as baud rate, I'd go through yet a third named pipe that I haven't otherwise mentioned.
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Re: How do I make device look like standard serial port

Postby support » Thu Apr 26, 2018 6:49 pm

Hello,

Short answer: No. There is no quick way to turn a Xillybus stream into a serial port-alike. Serial ports are rather special creatures in the Linux kernel, with special ioctls and whatnot.

I would use the pseudo-terminal devices (/dev/pty*) and pipe data between the Xillybus stream and the pseudo-terminals, and then direct the program that expects a TTY to the other side of the PTY. This requires a user-space daemon (socat?) to shuffle data, but it's probably the quickest way to get this up and running.

Regards,
Eli
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Re: How do I make device look like standard serial port

Postby helmutforren » Fri Apr 27, 2018 11:43 am

Thanks, Eli. I believe there was a not-getting-notifications snafu for me and this thread. Thanks for pointing out in the other thread.

So I read your short answer. I see you mentioning pty. I have gotten similar pty advice from linuxquestions.org. So I have my marching orders...

Hearing the "no" from the horse's mouth (hey, I love horses, no negativity intended) is a good thing to have. That means I won't start marching unaware of the ready-made solution I didn't see.

One more thing, please. Over at linuxquestions.org I have one fellow pointing me to pty. I have another fellow with whom I'm having a devil of a time communicating. The best I can fathom right now is that he's saying Xillybus will produce a single device that can be used for reading AND writing, which I will call /dev/xillybus_rxtx. My reading of the doc says this isn't true. Xillybus will produce at least *two* devices, such as the "Hello, world" example /dev/xillybus_read_8 and /dev/xillybus_write_8. It then becomes incumbent upon *me* to merge those into a single /dev/pty*, and per your comment, using a user-space daemon (socat?) to shuffle data.

-Helmut
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Re: How do I make device look like standard serial port

Postby support » Fri Apr 27, 2018 12:30 pm

Hello,

The answer is that both options are correct: The out-of-the-box bundle indeed creates, among others, device files that are unidirectional, e.g. /dev/xillybus_read_8 and /dev/xillybus_write_8. However you can set up and download a custom Xillybus IP core at the site (the "IP Core Factory"), and define a bidirectional device file, which may very well have the name /dev/xillybus_rxtx (or whatever name you choose). Which is probably a good idea in your case.

For the record, the other thread is: https://www.linuxquestions.org/question ... ?p=5847709

Regards,
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Re: How do I make device look like standard serial port

Postby Guest » Wed May 02, 2018 1:57 pm

Ah ha. Thanks very much, Eli, sincerely. So indeed it would be an optimization to user single bi-directional named pipes whenever I can. (For reference, a google of "can a linux named pipe be bi-directional" gives warnings and advice.)

It turns out that the pty method won't work well for me because I must be quickly responsive to multiple [man page IOCTL_TTY(2)] calls. I have come up with a strategy. Rather than repeat the question here, I'll link to it over in linuxquestions.org. Be aware that I wrote this BEFORE reading here from you about bi-directional pipes. The general solution remains the same.

Would you please be so kind, Eli, to visit over there and tell me your thoughts -- either over there or right here. Thanks very much.

The link is: https://www.linuxquestions.org/question ... ost5849739

(on the side, I'm not getting email notification of your replies. Did I miss a setup somewhere? I don't see a checkbox on the actual post as some forums have.)
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Re: How do I make device look like standard serial port

Postby support » Wed May 02, 2018 2:17 pm

Hello,

Why did the pty way fail? You didn't mention what kind of ioctl() calls the "fake" TTY needs to be responsive to.

Anyhow, I would remain with the pty concept, possibly copying the existing pty sources and making changes to match my needs. The less you do in kernel space, the better.

As for subscribing to this thread: You posted your last message as a guest user, which probably explains why you didn't have any related checkboxes.

Regards,
Eli
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Re: How do I make device look like standard serial port

Postby helmutforren » Wed May 02, 2018 5:23 pm

Eli,

I sincerely appreciate your persueing this.

The needed ioctl() include ioctl(intr_fd,TIOCMGET,&l_status), ioctl(intr_fd,TIOCMSET,&l_status), and ioctl(intr_fd, TIOCMIWAIT, TIOCM_CTS). Note that the last of those is blocking and is used to respond quickly to an event, as if one would respond to an interrupt. These calls are in fact for watching for an external event signaled by the DCD serial line. In addition, other code that uses the port for serial communications calls tcsetattr() and tcgetattr().

My best understanding of how to handle this with pty's is to have my user-space program open not only the master side of a pty, but also the same slave side as the application code above. This is because the TERMIOS data related to tcsetattr() and tcgetattr() doesn't get through the pty to the master side. (And I had not yet even considered those specific ioctl's when I built this understanding.) However, I don't know of a way to make my user-space program react immediately to the tcsetattr(), for baud rate setting for example, without polling. I'd prefer not to poll. Furthermore, my cohort at work who's in charge of the application (long term company IP) wants to be able to use more and more of what I find at both man pages IOCTL_TTY(2) and TERMIOS(3). Well, I understand how to work on a character device loadable kernel module, I even have my own model. I understand how to expand or adapt it to respond to all these things. But I do not understand how to get the info and timeliness across the pty. If you can clarify that, then maybe I'll like the pty solution again...

Now, you mentioned copying existing pty sources. Are those for kernel space or user space? Note I do have an existing kernel space driver that was written for our previous gen product that had similar FPGA peripheral devices but not Xillybus.

(This time I'm logged in and see the fourth checkbox to notify me. I guess I got timed out, and most places you can't post when not logged in and therefore get prompted to log in.)
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Re: How do I make device look like standard serial port

Postby support » Wed May 02, 2018 7:10 pm

Hi,

I've actually never programmed anything for pty, so I don't know if an event like DCD is passed through -- but I would be surprised if it did, given that pty's are usually used for faking a TTY so it can be used with software that expects such.

The sources for the real pty devices are in Linux kernel. It still sounds like a good starting point to me, but I'm not at all sure on how to integrate its derived driver into your project. I now realize there are a lot of factors involved.

Regards,
Eli
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Re: How do I make device look like standard serial port

Postby Guest » Fri May 11, 2018 7:52 pm

Eli,

You know Dan F. from the company I'm working for. Our company will be purchasing something or other so that we can use Xillybus. This purchase might have already happened.

As I develop my code, it would be easier and FASTER for me to use your IP generator to build a SMALL version of the final design. Is it acceptable to generate multipe versions over time, with only the single purchase? For example, I might first generate one with just four fifos (two in, two out; one pair for serial, one pair for C&C). This should build faster and help in many ways. By the end, I'll generate one with dozens and dozens and dozens of fifos.

-Helmut
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Re: How do I make device look like standard serial port

Postby support » Fri May 11, 2018 8:19 pm

Hello,

The licensing conditions given at the relevant part of the site apply to IP cores downloaded from the IP Core Factory as well. As such, there's no limitation on the number of IP cores that are configured, downloaded and tried out under the Evaluation License, as long as its terms apply.

However the Production License, once obtained, relates to a single IP Core ID. It's a unique number given to each IP core configuration (it can be found in the Readme file of the downloaded custom IP core bundle).

Regards,
Eli
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