customized the xillybus IP core problem in vivado

Questions and discussions about the Xillybus IP core and drivers

customized the xillybus IP core problem in vivado

Postby liwenz » Thu Aug 02, 2018 2:50 am

Hi,

I have customized the xillybus IP core .

As per the steps, I have replaced xillybus_core.v, xillybus.v and xillybus_core.ngc file with that from the downloaded bundle. Everything seems perfect, the opt-design is failing.

I have attached a snapshot of the opt-design error

[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: xillybus_ins/xillybus_core_ins/unitw_6_ins/unitw_6_active_glue_set_SW0.

i use vivado 2018.1

thanks
liwenz
liwenz
 
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Re: customized the xillybus IP core problem in vivado

Postby support » Thu Aug 02, 2018 7:07 am

Hello,

The said error is the tools admitting to have optimized away logic, and then missing it at a later stage. With Xillybus, this typically happens when you've added a stream on the custom IP core, but not made any use of it in your application logic. Or even no reference.

In other words, you should also edit xillydemo.v/.vhd to relate to the new IP core and its streams. Note that there's an instantiation template in the bundle to make this easier.

Regards,
Eli
support
 
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Re: customized the xillybus IP core problem in vivado

Postby liwenz » Fri Aug 03, 2018 12:45 am

thank you very much!
liwenz
 
Posts: 4
Joined: Thu Aug 02, 2018 2:40 am


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