customized the xillybus IP core problem in vivado
Posted:
Hi,
I have customized the xillybus IP core .
As per the steps, I have replaced xillybus_core.v, xillybus.v and xillybus_core.ngc file with that from the downloaded bundle. Everything seems perfect, the opt-design is failing.
I have attached a snapshot of the opt-design error
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: xillybus_ins/xillybus_core_ins/unitw_6_ins/unitw_6_active_glue_set_SW0.
i use vivado 2018.1
thanks
liwenz
I have customized the xillybus IP core .
As per the steps, I have replaced xillybus_core.v, xillybus.v and xillybus_core.ngc file with that from the downloaded bundle. Everything seems perfect, the opt-design is failing.
I have attached a snapshot of the opt-design error
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: xillybus_ins/xillybus_core_ins/unitw_6_ins/unitw_6_active_glue_set_SW0.
i use vivado 2018.1
thanks
liwenz