dma buffers function like fifo?

Questions and discussions about the Xillybus IP core and drivers

dma buffers function like fifo?

Postby liwenz » Wed Aug 15, 2018 3:01 am

Hi,

i use xillybus to samle adc signal.but not always read the singal data on the linux host.only read on some error moment´╝îlike oscilloscope capture.
if DMA buffers are overflowed,but i will not read on the host.should the dma buffers function like fifo?hold the newest data,discard the old data?

thanks
liwenz
liwenz
 
Posts: 4
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Re: dma buffers function like fifo?

Postby support » Wed Aug 15, 2018 3:55 am

Hello,

Technically speaking, if the DMA buffers get full, the Xillybus IP core at the FPGA stops transporting data from the FPGA's FIFO into these buffer, and soon the FPGA overflows. Once the host starts reading the data from the device file, DMA buffers are made vacant, and the IP core resumes transporting data, taking the FPGA's FIFO out of the overflow condition. But as a result, the data that arrives to the host will not be continuous.

The question is what the nature of the trigger is. If it's an event taking place at the host, you may simply open the device file when on the trigger event and start reading data from that moment on. The FIFO's reset input should be connected to the respective Xillybus stream's inverted open signal, so when the device file is closed, the FIFO is held reset. This gives a clean start.

If the trigger event can be detected on the FPGA, it's also possible to begin pushing data into the FIFO only after the trigger has occurred.

However if the trigger is known only in retrospect, and you need the data before the trigger, then you should read the data continuously, keep it in a large RAM buffer in the application program, and then fetch the pre-trigger data from that RAM buffer once the trigger is detected. Reading data directly into a RAM buffer is a low-CPU task, so there's no significant penalty for this solution, even at the highest bandwidths. The fifo.c example code, which comes along with the example programs (which is also explained in Xillybus' programming guides), can be used as a starting point for implementing such a RAM buffer (but it needs some modification, of course).

Regards,
Eli
support
 
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Re: dma buffers function like fifo?

Postby liwenz » Wed Aug 15, 2018 5:37 am

hello,Eli

thank you very much.
the trigger event is detected on the FPGA, and we need the data before the trigger, and the data after the trigger.
as you say ,the only way : we should read the data continuously, keep it in a large RAM buffer in the application program.

Regards,
liwenz
liwenz
 
Posts: 4
Joined: Thu Aug 02, 2018 2:40 am


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