Eli,
First, please excuse me for my poor wording. The file in question is indeed a Xilinx (C) file. It's just that I first got it by downloading your example. It doesn't mean you're responsible, but it does mean you might be knowledgeable.
In fact, I just found
http://billauer.co.il/blog/2017/02/pipe ... ie-xilinx/ where you dance around in this file in detail. Unfortunately, you don't address my specific issue. You *do*, however, make me think that this pclk_sel signal indeed is fairly static with respect to the clocks, and that I should be able to ignore this timing failure. Again, I would have thought that the verilog (* *) flags or the constraints would cause the tool to ignore the timing failure, but it hasn't. I'm just nervous about marking it for ignore myself! I'm hopeful that my need to move the 4x lanes to a different GTX pulled a constraint out from applicability. I can't find evidence of that in the critical and regular warnings however.
Thanks,
-Helmut