37mb data to be write and read

Questions and discussions about the Xillybus IP core and drivers

37mb data to be write and read

Postby Guest » Mon Sep 03, 2018 2:59 pm

hi... i have to use two data files one with small size while the other is large file of complex matrix. the file has 575 columns and 18689 rows with floating point numbers and its size is around 38Mbs. now i want to know is it possible to send and receive these files using the loopback fifo without modifying the demodesign by just using these lines

" fdr = open ("dev/xillybus_read_32", O_RDONLY);
fdr = open ("dev/xillybus_write_32", O_WRONLY); "
and properly opening and closing the files. ?

or i have to edit the design and edit the vhdl code of the fifo in order to read such large file of data? simply put do i have to make changes in the demodesign in Vivado or just writing a c/c++ code is enough.

Thanks
Guest
 

Re: 37mb data to be write and read

Postby support » Mon Sep 03, 2018 3:45 pm

Hello,

If all you want is to send the data towards the FPGA and read exactly the same data back from it, no changes are required on the logic side.

However please note that you should have different threads or processes running simultaneously for reading and writing. In particular, don't expect to write all data in one go, and only after that read it back. It's a common mistake to write programs that write first, read later.

You will get away with this mistake if the DMA buffers are large enough to contain all data in flight, but I'm not sure the demo bundle supplies that. You can always create a custom IP core if you really insist on write first, read later. Anyhow, the correct and practical way is simultaneous write and read.

Regards,
Eli
support
 
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