Xillybus Lite

Questions and discussions about the Xillybus IP core and drivers

Xillybus Lite

Postby Guest » Tue Sep 11, 2018 1:52 pm

Dear Support,


For the project that I'm doing I am using the xillinux 2.0, and I need to transfer flags from the processor to the PL, so I've try to use the Xillybus Lite, for transferring small amount of data.
I read the manual ( http://xillybus.com/downloads/doc/xillybus_lite.pdf ) and try to use the demo (i'm not strong in C programming so I have some questions ) .
I don't understand how is the address is selected. and how can I change/control it. I saw that the 4 numbers are writing (0 to 3) to the first address (dose every 8 bit are one digit and all the 4 digits are one memory register or 32 bit? or every digit is the address and the number that writing in the memory?) but when I try to use the information from the PL like suggested at the manual couldn't access it (translate it to VHDL):

proress(user_clk)
if (rising_edge(user_wren) and user_addr(6 downto 2]="00101:) then
myregister <= user_wr_data;

I thought that my only issue that is the fact that I don't understand the address, so I've try to use "don't care" insted of specified address. and still no good.
proress(user_clk)
if (rising_edge(user_wren) and user_addr(6 DOWNTO 2)="-----")
myregister <= user_wr_data;


Thanks,
Adir
Guest
 

Re: Xillybus Lite

Postby support » Tue Sep 11, 2018 6:06 pm

Hello,

This question should be asked in Xilinx' forum, and not here, as it relates to understanding rather basic VHDL concepts. But since we're at it, here's the example code from xillydemo.vhd explained:

Code: Select all
process (user_clk)
  begin
    if (user_clk'event and user_clk = '1') then
      if (user_wstrb(0) = '1') then
        litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
      end if;


The process (user_clk) + if (user_clk'event and user_clk = '1') part is a template, which together means that the statements that follow should happen on a rising edge of user_clk. The mix-and-match you've done between a process on user_clk and a rising edge of user_wren has no proper translation into logic, and breaks the rules of synchronous design. In particular because you never ever want to detect a rising edge of anything else than a clock or a dedicated asynchronous signal, like a reset (it's about glitches).

The if (user_wstrb(0) = '1') part checks the state of user_wstrb's bit 0 at the event of a rising clock (because of the foregoing process / if), and if it's 1, then the register is updated, on that rising clock. Actually, it's an array, so we get a synchronous RAM.

I'm not sure how much this helped. What you really need is to grasp the basics of synchronous design with VHDL, and the xillydemo.vhd example will be crystal clear. That's where I would put the money if I were you.

Regards,
Eli
support
 
Posts: 623
Joined: Tue Apr 24, 2012 3:46 pm

Re: Xillybus Lite

Postby Guest » Wed Sep 12, 2018 2:41 pm

Hi Eli,

Thank you for the quick respond.
I understand my mistake, the only reason Iv'e done so is because of the Xillybus Lite manual .
I will read the VHDL code of the Xillybus Lite, it's looking pretty clear.

Thank you again, for your help.
Guest
 


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