Am I preventing Xillybus/PCIe from establishing a link?

Questions and discussions about the Xillybus IP core and drivers

Re: Am I preventing Xillybus/PCIe from establishing a link?

Postby Guest » Fri Dec 13, 2019 10:38 am


Any further resolution to this thread? I am looking at Xillybus for an embedded board that uses PCIe over cable. Tandem PCIe with updates will be essential. I see another thread here with issues regarding Tandem PCIe as well. Nominally since I am powered externally, I can boot up completely before bringing up the host PC, but I will need to reconfigure the FPGA over PCIe. I know I have to deal with those specific active configuration I/O bank requirements. But any reason why the Xillybus IP would have an issue with Tandem PCIe with updates, i.e, reconfiguration through MCAP over PCIe, keeping the core configuration alive?


Re: Am I preventing Xillybus/PCIe from establishing a link?

Postby support » Fri Dec 13, 2019 11:06 am


Running a PCIe interface with Xillybus is no different from any PCIe endpoint. If you unload Xillybus' driver prior to unloading the FPGA, there's no problem that it goes away for a while.

Be sure however to re-enumerate the PCIe bus after loading the new FPGA bitstream.

Alternatively, you may use partial reconfiguration for loading the application part only, while keeping the PCIe link up (including Xillybus' core). A Xillybus stream can be a handy way to transfer the bitstream data. The clear advantage is that pretty much everything remains stable.

I have no personal experience in neither TANDEM nor partial reconfiguration. However my hunch is that the latter solution will be easier in the long run, in particular since you don't need to re-enumerate the bus.

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