The Xillybus Forum

Hello,

Actually, it's much worse. It gets stuck really early.

Sorry. This was a completely silly idea. One can't swap the data just like that, because the TLP header information gets messed up.

So what I can suggest at this point is to edit the driver to swap the byte order of the data as it's interpreted by the ISR. I suppose one of the kernel built-ins cpu_to_be32()/be32_to_cpu()/cpu_to_le32()/le32_to_cpu() will do the trick. Since all processing of the data from the message buffer is done in the ISR, that should be enough.

The data may arrive swapped as well, but if you use a 32-bit stream, I guess swapping of the data wires will help.

Unfortunately, big Endian is quite uncommon, so Xillybus doesn't support it so well.

Regards,
Eli

support wrote:So what I can suggest at this point is to edit the driver to swap the byte order of the data as it's interpreted by the ISR. I suppose one of the kernel built-ins cpu_to_be32()/be32_to_cpu()/cpu_to_le32()/le32_to_cpu() will do the trick.

Yes, it works now, thank you. We've swatted the bytes in xillybus_isr.