Problem while integrating two user ipcores with xillybus PCI
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In my project I need to implement encryption and decryption algorithms with xillybus PCIe using vivado tools. Since I am new to the FPGA stuff, I am following non-HDL documentation of xillybus PCIe. I successfully implemented encryption ip core and tested using xillybus PCIe. The name of top level function of encryption “xillybus_wrapper” and decryption is “decrpt_wrapper”. When I am including both encryption and decryption ip cores, even my encryption ip core also not working with PCIe. I have read in xillybus website that, the name of the top level function must be always “xillybus_wrapper” and should not be changed. I assume that, the problem is top level function naming. Someone please assist me how to move further if I need to integrate two user logic ip core with xillybus PCIe.