Problem with (ATX)PLL and fPLL on Cyclone 10GX DevKit

Questions and discussions about the Xillybus IP core and drivers

Problem with (ATX)PLL and fPLL on Cyclone 10GX DevKit

Postby Guest »

Hello,

we want to use a Cyclone 10GX Development Kit Board to transfer data from a PC to a custom optical link. Xillybus does a great job connecting the boart to the PC via PCIe.
But when I add an (ATX)PLL or fPLL to the project (completely independent from the Xillybus-stuff) I can't get it to lock to the externally applied clock. An IOPLL works without problems (but cannot be used for the transceivers).
Removing xillybus_ins immediately fixes the misfunction of the PLLs. Already tested with different clock-pads and frequencies.

Any idea what I am doing wrong or could try?

Best, Chris
Guest
 

Re: Problem with (ATX)PLL and fPLL on Cyclone 10GX DevKit

Postby support »

Hello,

Transceivers have their own clocking resources with rules on which PLL can be used with which transceiver and what routing resources can be used etc. Odds are that the transceivers you've allocated for the optic channel require clocking resources that conflict with the PCIe's transceivers, and things get messy. I'm surprised that you didn't get some really nasty warnings from the tools.

You might delve into the documentation on the matter, or alternatively try to narrow the PCIe lane width, as long as your bandwidth requirements are met. Note that each Gen1 lane gives you ~200 MB/s of payload bandwidth, a Gen2 lane ~400 MB/s and Gen3 gives ~800 MB/s. Also note that Xillybus' eval bundle's setting isn't Gen3, so you can reduce lane count and increase speed without changing performance.

It might be helpful to reduce the speed to Gen1 only. Not sure about this, but that requires only one data clock rate, which might ease on the clock resources. A shot in the dark if everything else fails.

Xillybus' IP core is indifferent to the PCIe parameters (on Cyclone 10GX) as long as the interface width remains the same, so just change the PCIe block's setting and re-implement.

Regards,
Eli
support
 
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Re: Problem with (ATX)PLL and fPLL on Cyclone 10GX DevKit

Postby Guest »

Hello Eli,

thank you for your thoughts and suggestions.
The problem was due to the setup of my test:
- the developmentboard was tested outside a PC to check and improve the fiber-interface and to be able to access testsignals
- so the FPLL used by Xillybus/PCIe did not get a clock-signal
- seems that this "floating" FPLL hindered all other PLLs in the transceiver-blocks to lock.

Best regards,
Chris
Guest
 


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