An error was encountered initializing the timing graph

Questions and discussions about the Xillybus IP core and drivers

An error was encountered initializing the timing graph

Postby Guest » Thu Oct 17, 2019 3:40 am

I am getting below error while using xillybus pcie custom ip core for VCU108 with my user logic ip core. Please assist me in this. Thank you





INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048_SM_V.v:28]
INFO: [Synth 8-6155] done synthesizing module 'mod_mult_2048_SM_V_ram' (47#1) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048_SM_V.v:9]
INFO: [Synth 8-6155] done synthesizing module 'mod_mult_2048_SM_V' (48#1) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048_SM_V.v:64]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1288]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1290]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1292]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1314]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1316]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1318]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:1344]
WARNING: [Synth 8-6014] Unused sequential element ap_return_preg_reg was removed. [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:419]
INFO: [Synth 8-6155] done synthesizing module 'mod_mult_2048' (49#1) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_mult_2048.v:10]
INFO: [Synth 8-6155] done synthesizing module 'mod_exp' (50#1) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/mod_exp.v:10]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:743]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:783]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:785]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:787]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:807]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:809]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:811]
INFO: [Synth 8-6155] done synthesizing module 'xillybus_wrapper_4' (51#1) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ipshared/57b4/hdl/verilog/xillybus_wrapper_4.v:12]
INFO: [Synth 8-6155] done synthesizing module 'blockdesign_xillybus_wrapper_4_0_1' (52#1) [c:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/ip/blockdesign_xillybus_wrapper_4_0_1/synth/blockdesign_xillybus_wrapper_4_0_1.v:58]
INFO: [Synth 8-6155] done synthesizing module 'blockdesign' (53#1) [C:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/blockdesign/synth/blockdesign.v:13]
INFO: [Synth 8-6155] done synthesizing module 'xillydemo' (54#1) [C:/Users/sarve/Desktop/Federate_system_learning/xillybus-eval-virtexultrascale-2.0d/blockdesign/src/xillydemo.v:1]
WARNING: [Synth 8-3331] design mod_mult_2048_SM_V has unconnected port reset
WARNING: [Synth 8-3331] design mod_mult_2048_Y_V has unconnected port reset
WARNING: [Synth 8-3331] design mod_mult_2048_X_V has unconnected port reset
WARNING: [Synth 8-3331] design mod_mult_2048_M_V has unconnected port reset
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[8]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[7]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[6]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[5]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[4]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0]
WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port WR_EN_INTO_LOGIC
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port WR_RST_INTO_LOGIC
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port RD_EN
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port SRST_FULL_FF
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port WR_RST_BUSY
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port EMPTY
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port RAM_RD_EN
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port ALMOST_EMPTY
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[8]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[7]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[6]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[5]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[4]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[3]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[2]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[1]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH[0]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[8]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[7]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[6]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[5]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[4]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[3]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[2]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[1]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_ASSERT[0]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[8]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[7]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[6]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[5]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[4]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[3]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[2]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[1]
WARNING: [Synth 8-3331] design wr_logic__parameterized0 has unconnected port PROG_FULL_THRESH_NEGATE[0]
WARNING: [Synth 8-3331] design rd_fwft has unconnected port SRST
WARNING: [Synth 8-3331] design rd_fwft has unconnected port SAFETY_CKT_RD_RST
WARNING: [Synth 8-3331] design rd_fwft has unconnected port RAM_ALMOST_EMPTY
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[8]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[7]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[6]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[5]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[4]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0]
WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port RD_EN_INTO_LOGIC
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port RD_RST_INTO_LOGIC
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port RD_RST_BUSY
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port RAM_WR_EN
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port RST_FULL_FF
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port ALMOST_FULL_FB
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port FULL
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[8]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[7]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[6]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[5]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[4]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[3]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[2]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[1]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port WR_PNTR_PLUS1_RD[0]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[8]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[7]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[6]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[5]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[4]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[3]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[2]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[1]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH[0]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[8]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[7]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[6]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[5]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[4]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[3]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[2]
WARNING: [Synth 8-3331] design rd_logic__parameterized0 has unconnected port PROG_EMPTY_THRESH_ASSERT[1]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:01:05 ; elapsed = 00:01:09 . Memory (MB): peak = 2655.758 ; gain = 2277.035
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:14 ; elapsed = 00:01:19 . Memory (MB): peak = 2655.758 ; gain = 2277.035
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:14 ; elapsed = 00:01:19 . Memory (MB): peak = 2655.758 ; gain = 2277.035
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 43 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xcvu095-ffva2104-2-e
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Caught ... exception.
ERROR: [Timing 38-246] Caught exception 'ERROR: [Timing 38-432] Unexpected exception thrown which building timing graph
' while reading timing library and applying constraints.
Resolution: For technical support on this issue, please visit http://www.xilinx.com/support
INFO: [Common 17-83] Releasing license: Synthesis
83 Infos, 123 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Timing 38-17] An error was encountered initializing the timing graph. Analysis will not be performed.
Resolution: For technical support on this issue, please visit http://www.xilinx.com/support
INFO: [Common 17-206] Exiting Vivado at Thu Oct 17 11:32:10 2019...
Guest
 

Re: An error was encountered initializing the timing graph

Postby support » Thu Oct 17, 2019 3:55 am

Hello,

I take it that you managed to build the project properly with the downloaded ZIP bundle, and this happened only when applying the custom IP core.

It's a bit difficult to relate to the error directly, however these thing tend to happen due to a confusion on which files Vivado consumes to implement the project. In other words, you probably did replace the file as instructed, but Vivado keeps using old files. It has this thing about making copies of the source files and using them instead.

A full project reset may help, or just some plain investigation on what went wrong. If this fails, I'd suggest starting from the ZIP bundle, replace / edit its files as necessary, and launch the Tcl script on the updated bundle. Note that it's quite easy to add your own sources to the project by editing the Tcl script.

This is, by the way, how I personally work with Vivado projects: Keep a small set of files (under version control) and then I rebuild the project every now and then to ensure I don't accumulate quirks in the project's settings. As well as outdated files.

Regards,
Eli
support
 
Posts: 733
Joined: Tue Apr 24, 2012 3:46 pm


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