Simple read/write memory interface

Questions and discussions about the Xillybus IP core and drivers

Simple read/write memory interface

Postby Guest » Sun Oct 20, 2019 1:49 am

Code: Select all
mem_reg_16 mem_reg_16 (
    .clk      (bus_clk           ),
    .din      (user_w_mem_16_data),
    .we       (user_w_mem_16_wren),
    .re       (user_r_mem_16_rden),
    .addr     (user_mem_16_addr  ),
    .dout     (user_r_mem_16_data),
always @(posedge clk) begin
    if (we)
        mem_reg_16[addr] <= din;
    if (re)
        dout <= mem_reg_16[addr];

In a simple read/write memory interface on xillybus, if I need to delay the `read` and `addr` signal by one clock to improve timing, the `dout` signal will also be delayed by one clock. But in this case, memory cannot be correctly readout through xillybus. I am wondering is there a method to solve this?

Re: Simple read/write memory interface

Postby support » Sun Oct 20, 2019 4:06 am


Please refer to to section 3.4 of the Xillybus FPGA designer’s guide, which deals with memory interface signals:

To give the application logic some time to retrieve the data, you may assert the "empty" signal after each read operation, hence preventing a read cycle before the next data element is ready.

But what if the address changes? This is what section 3.4 discusses: The idea is that the "empty" signal can also be asserted even after _addr_update marks an address change. Once again, gives the application some time.

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