Not able to write data to FPGA (Virtex 7)

Questions and discussions about the Xillybus IP core and drivers

Not able to write data to FPGA (Virtex 7)

Postby Guest » Sun Feb 23, 2020 3:13 pm

Greetings!

I am inputting 2 images of size 1292*960 by converting them into one array of size 1292*960*2, I get correct output from FPGA and everything works fine but when I increase the size of both images to 1292*2000 (I input total 1292*2000*2 inputs of 8 bit each) my code does not run i.e it does not even go inside int main().

I have increased the no. of buffers to 512 from the IP Core factory (64MB buffer) but it does not seem to work. Even the loopback is not working when using xillybus_read_8 and xillybus_write_8. I have also increased the memory allocation using malloc to a sufficiently large size. I am using Xilinx Virtex-7 (Gen3 PCIe block).

Help is really appreciated!!

Thanks,
Shashwat
Guest
 

Re: Not able to write data to FPGA (Virtex 7)

Postby support » Sun Feb 23, 2020 3:38 pm

Hello,

It seems like there are a few details missing in your description. What are you attempting to do? When you say "inputting images", from where and to where? From the notion that main() isn't invoked, I guess that there's HLS involved (or else how could that make sense?).

So could you please come forward with a more comprehensive picture of what you're trying to do, in what way it fails, and what makes you conclude that the issue is X or Y?

Regards,
Eli
support
 
Posts: 733
Joined: Tue Apr 24, 2012 3:46 pm

Re: Not able to write data to FPGA (Virtex 7)

Postby shashwat » Mon Feb 24, 2020 9:29 am

Hello,

I have a text file of pixel values. And from that text file I am reading the pixels and storing them in an array and then sending it to FPGA.

I have dumped the bitfile on FPGA and then I restart my system so that I get xillybus drivers for 64bit write and read. After restarting I run my c++ code (shown below). But for an image of size 1292*2000, this codes main is not evoked. (Worked for 1292*960 image).

The size of the text file is 9.5 MB. Since there are 2 text files total size FPGA will read is 19 MB.

#include <opencv2/opencv.hpp>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdint.h>
#include <time.h>
#include <unistd.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#include <sys/time.h>
using namespace cv;
using namespace std;
#define chunk 1
#define img_w 1292
#define img_h 2000
#define im_l "left_kitti_pad.txt"
#define im_r "right_kitti_pad.txt"

void allwrite(int fd, unsigned char *buf, int leng);
void allread(int fd, unsigned char *buf, int leng);

int l_image[img_h*img_w];
int r_image[img_h*img_w];
unsigned char bothimg[2*img_h*img_w];
unsigned char *buf=(unsigned char *)malloc(100000000 * sizeof(unsigned char*));
int main()
{
int fdr, fdw;
FILE *fp;
int i,j,inp;
clock_t start, end;
double total_cpu_time = 0;
double cpu_time_used;
struct timeval tv1, tv2;
int col=0;
int imgHeight=img_h;
int imgWidth=img_w;
//Reading both the images from text file
fp = fopen(im_l,"r");//l_image.txt
fscanf(fp,"%d",&inp);
for(i=0;i<imgHeight*imgWidth;i++){
l_image[i] = inp;
fscanf(fp,"%d",&inp);
if(feof(fp))break;
}

fp = fopen(im_r,"r");//r_mc.tct
fscanf(fp,"%d",&inp);
for(i=0;i<imgHeight*imgWidth;i++){
r_image[i] = inp;
fscanf(fp,"%d",&inp);
if(feof(fp))break;
}


fdr = open("/dev/xillybus_read_64", O_RDONLY);
if (fdr < 0) {
perror("Failed to open read Xillybus device");
exit(1);
}
fdw = open("/dev/xillybus_write_64", O_WRONLY);
if (fdw < 0) {
perror("Failed to open write Xillybus device");
exit(1);
}
long double t1;
int fcount = 0;
long long int len = 2000*1292*2;
long long int lenr = 1224*1996*2+16;
uchar* p = bothimg; // returns pointer to start of frame data.

j=0;
for(i=0;i<2*imgHeight*imgWidth;i=i+2){
bothimg[i]=(unsigned char)l_image[j];
j=j+1;

}
j=0;
for(i=1;i<2*imgHeight*imgWidth;i=i+2){
bothimg[i]=(unsigned char)r_image[j];
j=j+1;
}
for(int i=0;i<10;i++){
allwrite(fdw,p,len);
gettimeofday(&tv1,NULL);//to calculate fpga run time
allread(fdr,buf,lenr);
gettimeofday(&tv2,NULL);
unsigned short int* out= (unsigned short int*)buf;
for(j=0;j<1224*1996+8;j=j+4){
if(col==0){
for(i=j;i<2+j;i++){
printf("%d\n",*(out+i));
}
}
else{
for(i=j;i<4+j;i++){
printf("%d\n",*(out+i));

}
}
if(col==305){
col=0;
}
else
col++;

}

cpu_time_used = (double)(tv2.tv_usec - tv1.tv_usec - 100)/1000000 + (double)(tv2.tv_sec - tv1.tv_sec);
total_cpu_time += cpu_time_used;
printf(" \n %f \n", total_cpu_time);
}
return 0;
}

void allwrite(int fd, unsigned char *buf, int leng) {
int sent = 0;
int rc;

while (sent < leng) {
rc = write(fd, buf + sent, leng - sent);

if ((rc < 0) && (errno == EINTR))
continue;

if (rc < 0) {
perror("allwrite() failed to write");
exit(1);
}

if (rc == 0) {
fprintf(stderr, "Reached write EOF (?!)\n");
exit(1);
}

sent += rc;
}
}

void allread(int fd, unsigned char *buf, int leng) {
int readd = 0;
int rc;

while (readd < leng) {
rc = read(fd, buf + readd, leng - readd);

if ((rc < 0) && (errno == EINTR))
continue;

if (rc < 0) {
perror("read() failed");
exit(1);
}

if (rc == 0) {
fprintf(stderr, "Reached read EOF!? Should never happen.\n");
exit(0);
}

readd += rc;

}
}
shashwat
 
Posts: 1
Joined: Sun Feb 23, 2020 3:00 pm

Re: Not able to write data to FPGA (Virtex 7)

Postby support » Mon Feb 24, 2020 10:16 am

Hello,

What do you mean that the code's main isn't invoked? How do you know?

And in particular: If the main() isn't invoked, how could this issue be related to Xillybus? I mean, if that's indeed the case, then the Xillybus device files aren't even opened, so they couldn't have any influence on the software's flow.

Regards,
Eli
support
 
Posts: 733
Joined: Tue Apr 24, 2012 3:46 pm


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