kintex 7 fpga support pcie x8,5Gbps per lane?

Questions and discussions about the Xillybus IP core and drivers

kintex 7 fpga support pcie x8,5Gbps per lane?

Postby andylgh » Sat May 16, 2020 7:23 am

kintex7 fpga the bundle demo is pcie x8 and 2.5Gbps per lane, user can change to support pcie x8,5Gbps per lane or not?
andylgh
 
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Re: kintex 7 fpga support pcie x8,5Gbps per lane?

Postby support » Sat May 16, 2020 7:41 am

Hello,

Yes, it's possible to change the PCIe interface's lane count and speed. How to do this is explained in section 4.5 of the Getting started with the FPGA demo bundle for Xilinx document.

It's however pointless to change the lane rate to 5 Gbps (Gen2) in most cases, since this will not increase the data throughput obtained with the IP core, even with a revision B core. The demo bundle for XL cores, which goes up to 3.5 GB/s, has indeed the PCIe link set to Gen2 x 8, as that IP core is capable of utilizing the raw PCIe bandwidth of this setting.

Regards,
Eli
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