mem read interface question

Questions and discussions about the Xillybus IP core and drivers

Re: mem read interface question

Postby support » Thu May 21, 2020 3:22 pm

Hello,

If the neither the empty signal nor the data input change as a result of the read cycle, the rd_en signal can indeed be ignored. So controlling the empty signal only based upon _addr_update will do the work, however you won't be able to read more than a single memory cell this way.

Regards,
Eli
support
 
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Re: mem read interface question

Postby andylgh » Fri May 22, 2020 2:10 am

support wrote:Hello,

If the neither the empty signal nor the data input change as a result of the read cycle, the rd_en signal can indeed be ignored. So controlling the empty signal only based upon _addr_update will do the work, however you won't be able to read more than a single memory cell this way.

Regards,
Eli


in some applicaiton, if i want to use the the mem_intf bridge to axi4 lite to read and write reigister, is it possible?

host : lseek + write -> addr + wdata
host: lseek + read -> addr + rdata

write : i can use wren and the full to delay , if i capture wren i can active full to high ,only pull low when axi lite write done
read: i want to use addr_update,but when lseek + write in host also generate addr_update? is it any method to solve it?
andylgh
 
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Re: mem read interface question

Postby support » Fri May 22, 2020 10:00 am

Hello,

Yes, this is what I mentioned earlier: Because the FPGA side doesn't know if the addr_update is a preparation for a read or write, it must perform a read operation on the other bus to have the value prepared. One could get around this with some dirty trick maybe, but if this is an issue, I would suggest dropping the address interface altogether, and go for a command-data approach instead.

For example, say that you use a plain 32-bit Xillybus stream from the host to the FPGA to send commands. Bits [5:0] could be the address, and bit 31 could be the read/write flag: If it's 1, it's a write command, if it's 0, it's a read. And if it's a write command, set the value to write in bits [15:8], for example.

Then, if it's a read command, use a simple 8-bit FPGA to host stream to return the value when it's ready. You could put a FIFO inbetween and write the read data into the FIFO, or interface with the core directly, by manipulating the empty wire.

Plain, simple, and gives you full control over what's going on.

Regards,
Eli
support
 
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Re: mem read interface question

Postby andylgh » Fri May 22, 2020 10:46 pm

ok,thanks for your reply
andylgh
 
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