Is clk 50 and clk 125 required?

Questions and discussions about the Xillybus IP core and drivers

Is clk 50 and clk 125 required?

Postby Guest » Tue Jun 02, 2020 12:05 am

Hi,

I have a Cyclone IV GX development board which has no transceivers, so I'm wondering if the clk 50 and clk 125 are still needed?

Thanks.
Guest
 

Re: Is clk 50 and clk 125 required?

Postby support » Tue Jun 02, 2020 5:17 am

Hello,

If the board doesn't supply the 50 MHz and 125 MHz clocks, they can be generated from another free-running clock by virtue of a PLL. This is discussed in the IP Compiler for PCI Express User Guide, page 166:

https://www.intel.com/content/dam/www/p ... xpress.pdf

To make a long story short, the 125 MHz frequency is mentioned explicitly in the user guide, and it must be free-running and independent of the PCIe reference clock. However it can be derived from another free-running clock, and same goes for the 50 MHz clock.

There's a caveat, though: The PLL lock. The said user guide discusses this and explains how to deal with this issue.

Regards,
Eli
support
 
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