Simple Test: streamread /streamwrite do not work

Questions and discussions about the Xillybus IP core and drivers

Simple Test: streamread /streamwrite do not work

Postby mim » Wed Dec 30, 2020 8:20 am

Dear Xillybus Team,

I have an X4 Gen2 PCIe interface in a Xilinx FPGA board. After modifying your Demo bundle and successfully installing the windows driver, now I am going to test the functionality using part 4.3 of " Getting started with Xillybus on a Windows host" however nothing happened: I tried to track those two fifos input output, wren and rden in both fifos never goes high.

My desired test at the end will be testing the maximum achievable rate of streaming from FPGA to the host. I will connect a free run 32-bit 250Mhz counter to the input of FIFO (I guess it should be connected to the xillybus_read_32 interface) and saving it as a binary file at the host side.

Could you please help me?

Regards
Mim
mim
 
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Re: Simple Test: streamread /streamwrite do not work

Postby support » Wed Dec 30, 2020 11:38 am

Hello,

Since you mentioned a bandwidth check, I'll make sure you're aware of this page, which discusses some related topics:

http://xillybus.com/doc/bandwidth-guidelines

As for the lack of response in the loopback test, it's quite odd. Could you please detail exactly what you did, and what kind of changes you've made, if any?

And almost needless to say -- you did type some text on the windows running xillybus_write_8 and pressed ENTER -- right?

Regards,
Eli
support
 
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Re: Simple Test: streamread /streamwrite do not work

Postby mim » Sat Jan 02, 2021 8:37 am

Hello Elli,

Thank you for sharing that guideline. it is very great.

before proceeding to test the bandwidth, I should be able to successfully check your simple tests in loopback example.
What I have changed:
1.Changing on PCIe IP core: x8 to x4 / 2.5GT to 5GT / Device ID changed to EBEB
2.Changing on RTL codes: Changing related ports bit width from "7 downto 0 "to "3 downto 0" / Changing PCIE_LANE parameter from 8 to 4 / Adding ILA core and connecting FIFOs INs and OUTs ports to the ILA / bringing out the lnk_up port to see it via ILA core
3.Changing Device from KC705 dev board to the kintex k160.

That's all.
Actually the Timing stack (TNS) is negative ( :D ) about -0.258 while THS is not.

Regards,
Mim
mim
 
Posts: 3
Joined: Mon Dec 28, 2020 3:04 pm

Re: Simple Test: streamread /streamwrite do not work

Postby support » Sat Jan 02, 2021 9:31 am

Hello,

There's nothing in those changes that should prevent things from working properly, however sometimes making them causes a mistake, and that's when things break. So I would suggest trying to the original bundle, with the absolutely minimal changes possible. There is no problem leaving the link as x8, and have the upper 4 lanes connected to nothing in particular. The PCIe block negotiates the link width with the host, based upon what's connected. Hopefully that will work, and then it's a matter of gradually changing a working project to the desired target.

Having said that, it's quite unusual that the PCIe device is detected and then not works properly. Maybe some mishap while connecting the ILA to the FIFOs' ports?

And once again -- you did type something in the DOS windows running xillybus_write_8 and pressed ENTER...?

Also, I didn't complete understand this:
mim wrote:Actually the Timing stack (TNS) is negative ( :D ) about -0.258 while THS is not.


If you were referring to timing slack, and it was negative, it means that the design didn't meet timing constraints, in which case anything can happen. There's a Tcl script (showstopper.tcl) in the project that is supposed to prevent you from generating a bitstream file if this is indeed the case. So it's not clear what you meant with that.

Regards,
Eli
support
 
Posts: 754
Joined: Tue Apr 24, 2012 3:46 pm


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