WIN 10 Xillybus driver

Questions and discussions about the Xillybus IP core and drivers

WIN 10 Xillybus driver

Postby tozkoparan » Tue Aug 31, 2021 10:20 am

Hello

In our test environment, we have used Xillybus with PCs having WIN 7 without any problem for years.

In the last year, we upgraded the operating system of our test PCs to WIN10 and started to observe problems related to Xillybus driver.

For example, sometimes, our tests stop at 11:59 PM since Xillybus data communication from PCIe does not continue properly.

We cant any reason for stopping our tests at 11:59 PM.

Do you think that it can be related to Xillybus driver?

Because as I mentioned we did not observe this problem with WIN 7.

best regards.
tozkoparan
 
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Re: WIN 10 Xillybus driver

Postby support » Wed Sep 01, 2021 1:05 pm

Hello,

Xillybus' driver doesn't have anything that depends on the wall-clock time, so it's quite unlikely that this has anything to do with the driver (or the core, for that matter).

Could you please explain more accurately what you mean with that the test stops?

Regards,
Eli
support
 
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Joined: Tue Apr 24, 2012 3:46 pm

Re: WIN 10 Xillybus driver

Postby tozkoparan » Thu Sep 02, 2021 7:44 am

Hello and thanks for your answer

We are using a Xillybus core with 4 write channels and 8 read channels.
We use some of these channels for synchronous data transfer and some of them for asynchronous data transfer.

We observe that during our test an error related to the PCIe driver occurs at 11:59 PM.
After that somehow out test software can not send(or receive) data from synchronous channels.

Actually, there is also another type of error that occurs anytime. (not specifically at 11:59PM)
We observe that when this error occurs garbage data is collected to PC from one of the synchronous read channels.

And as I mentioned earlier, we were not encountering these types of errors when our test PCs have WIN7.

best regards
tozkoparan
 
Posts: 15
Joined: Wed Nov 15, 2017 6:59 am

Re: WIN 10 Xillybus driver

Postby support » Thu Sep 02, 2021 7:48 am

Hello,

Could you please elaborate on these two types of errors? What do you observe exactly?

Regards,
Eli
support
 
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Joined: Tue Apr 24, 2012 3:46 pm

Re: WIN 10 Xillybus driver

Postby tozkoparan » Thu Sep 02, 2021 8:29 am

Hello and thanks for the answer

We will try to give you more information soon.

Now, we want to mention that we observe errors when we investigate LOGs of WIN 10 on our test PCs.
When we open Event Viewer->Summary of Administrative Events we see that there are lots of Errors with Event IDs 304 and 307 and with source User Device Registration.
The time of these errors are 1:59:45AM, 2:59:45AM, 3:59:45AM...
We observe that these errors occur every hour.

Do you think that these error logs are relevant to the errors that occur in our tests?

best regards
tozkoparan
 
Posts: 15
Joined: Wed Nov 15, 2017 6:59 am

Re: WIN 10 Xillybus driver

Postby support » Thu Sep 02, 2021 8:36 am

And what do these log messsages say?

It's a bit difficult to help you solve a problem if you don't describe it and the details around it.

Regards,
Eli
support
 
Posts: 760
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Re: WIN 10 Xillybus driver

Postby tozkoparan » Thu Sep 02, 2021 8:47 am

Hello

Error logs are like
______________________________________________________________________
Event 304

Automatic registration failed at join phase
Exit code: Unknown HResult Error code: 0x801c001d
Server error:
Tenant type: undefined
Registration type: undefined
______________________________________________________________________

Evet 307

Automatic registration failed. Failed to look up the registration service information from Active Directory.
Exit code: Unknown HResult Error code: 0x801c001d

______________________________________________________________________

best regards
tozkoparan
 
Posts: 15
Joined: Wed Nov 15, 2017 6:59 am

Re: WIN 10 Xillybus driver

Postby support » Thu Sep 02, 2021 9:00 am

Hello,

The fact that you have recurring system errors with timestamps that resemble the time at which you have problems with your Xillybus-related application makes it seem like the culprit has been found. To me, it appears like the computer got very busy suddenly on these specific intervals, and stole computer resources (CPU most probably) from the program running your application.

As a result, the program wasn't able to read or write data quickly enough, and you got some kind of overflow or data starvation at the FPGA. Does your error indicate something of that sort? Do you have a mechanism in place to detect when the FIFO at the FPGA gets full, or when it's empty when the application logic needs data to be present?

If this is indeed the case, I would first look for a way to stop that Windows service, or at least stop it from hogging resources. As a second measure, maybe increasing the DMA buffer sizes in the IP core factory will help, as it makes the data flow more resilient to pauses in the program that processes the data.

But these are speculations on thin air, since I don't have any details on the nature of your error.

Regards,
Eli
support
 
Posts: 760
Joined: Tue Apr 24, 2012 3:46 pm

Re: WIN 10 Xillybus driver

Postby tozkoparan » Thu Sep 02, 2021 9:36 am

Hello

In our FPGA design on VC707, we have FIFOs connected to each write and read channel of Xillybus.
Overflow and empty signals of these FIFOs are connected to LEDs on VC707 to debug the data communication.
With these debug signals it is possible for us to understand whether the FPGA design has bugs or software collecting data from DMAs of Xillybus on PC has errors.

For the second error we mentioned before, after a couple of hour tests, suddenly,

When data(with fixed size) is read from one of the synchronous channels we are getting the data.
However, its content is not as we expected.
We are thinking that somehow software reading data from Xillybus DMAs in PC is disordering data. (Some kind of pointer problem)
Our test software stops here since the data is not as expected.
When we check our test LEDs in this situation, we observe that the FIFOs are not empty and there is overflow in the FIFOs.
This is also not correlated with our expectations.
Because even if software reading data from Xillybus DMAs makes errors our FIFOs must not go to overflow situation.
Since our FIFOs are not empty we understand that software reading data from Xillybus DMAs to PC has errors.
It does not get the correct amount of data from FPGA since the FIFOs are not empty.
This indicates a software problem. However, the overflow signal prevents us to come to a conclusion.

best regards
tozkoparan
 
Posts: 15
Joined: Wed Nov 15, 2017 6:59 am

Re: WIN 10 Xillybus driver

Postby support » Thu Sep 02, 2021 9:50 am

Hello,

Your description is consistent with a situation where your host software was halted momentarily because the computer suddenly got busy doing something else. If your software does some disk access while running (e.g. reading or writing data), that's even more likely to happen.

I suggest following the principles outlined in section 4.4 and 4.5 in the FPGA designer’s guide:

http://xillybus.com/downloads/doc/xillybus_fpga_api.pdf

Namely, to stop the data flow from the FPGA to the host with an EOF when an overflow occurs. This allows the host software to easily detect an overflow condition, and report it as such. Also, the logic accepting data from the host should stop fetching data when it reaches an underrun condition.

Both these measures ensure that if data is transmitted, it's correct. The fact that you get garbled data is most likely due to overflow / underrun. The possibility of a core or driver bug can be ruled out quite certainly, in particular as these have a very large mileage without any issue of that sort.

Regards,
Eli
support
 
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Joined: Tue Apr 24, 2012 3:46 pm

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