PCI-E BAR size for Xillybus
Posted: Hi,
how large the BAR should be set in the PCI-E IP Core for proper Xillybus operation?
how large the BAR should be set in the PCI-E IP Core for proper Xillybus operation?
Hello,
The Xillybus IP core should be used with the demo bundle for your target FPGA. The bundle includes a PCIe block, which has all settings made correctly, including the BAR size. Hence asking this question probably indicates a misunderstanding.
But the short answer is that the BAR size is 128 bytes.
Regards,
Eli