PCI-E BAR size for Xillybus

Questions and discussions about the Xillybus IP core and drivers

PCI-E BAR size for Xillybus

Postby Guest »

Hi,
how large the BAR should be set in the PCI-E IP Core for proper Xillybus operation?
Guest
 

Re: PCI-E BAR size for Xillybus

Postby support »

Hello,

The Xillybus IP core should be used with the demo bundle for your target FPGA. The bundle includes a PCIe block, which has all settings made correctly, including the BAR size. Hence asking this question probably indicates a misunderstanding.

But the short answer is that the BAR size is 128 bytes.

Regards,
Eli
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