Implementing _read() and _write()

[Guest]

Hi all,

I just want to get confirmation on what are admittedly stupid questions with implementing the _read() and _write() properly

First of all with writing to the FPGA,
if I am simply using the _write() function to send a single byte to act as a start or stop signal on the FPGA side, is something like this appropriate?

numbytew = 1;
char bufw = 0xFF;
rcw = _write(fdw, bufw, numbytew);

With reading from the FPGA,
let's say for now I simply want to save the data read from the FPGA onto a file as it's read in, would I simply need to do something like this?

rcr = _read(fdr, bufr, numbyter);
rcfile = _write(file, bufr, rcr);

Or would I need to make a function similar to allwrite in the demoapps?

Thanks!

[support]

Hello,

First of all with writing to the FPGA,
if I am simply using the _write() function to send a single byte to act as a start or stop signal on the FPGA side, is something like this appropriate?

numbytew = 1;
char bufw = 0xFF;
rcw = _write(fdw, bufw, numbytew);

Yes, this is OK. In principle, you should check the value of @rcw to ensure no error has occurred, but other than that, it's fine.

Then we have the question whether you want _write() to return before the byte has arrived to the application logic on the FPGA, or if you want it to wait until this happens. For the former case, use an asynchronous stream ("Data acquisition / playback" at the IP Core Factory) or a synchronous stream ("Command and status") for the latter.

With reading from the FPGA,
let's say for now I simply want to save the data read from the FPGA onto a file as it's read in, would I simply need to do something like this?

rcr = _read(fdr, bufr, numbyter);
rcfile = _write(file, bufr, rcr);

Or would I need to make a function similar to allwrite in the demoapps?

The code you wrote will work most of the time. But I would strongly suggest to follow the guidelines in the docs and the examples in demoapps. Once again, be sure that @rcr is strictly positive and use something like allwrite() for writing. It's a small effort that avoids a small risk to waste a lot of time.

Regards,
Eli

[Guest]

Thanks Eli!

Yeah I do have those checks in my actual code, I just put a small snippet for the sake of simplicity

Best regards

[Guest]

Hello again,

first of all, I would like to mention that for the _write() to work in my previous post, &bufw needs to be the argument in the _write() function.

After finishing writing the software and firmware, I am running into an issue reading data from the fpga with the error:
"_read() failed: invalid argument" and I'm hoping to get some insight as to what the cause is. Below is the snippet of code for the write and following read function:
int numbytew = 1, numbyter = 40;
unsigned char bufw;
unsigned char *bufr;
case 2 :
printf("case 2: set capture\n");
bufw = 0xFF;
rcw = _write(fdw, &bufw, numbytew);
if ((rcw < 0) && (errno == EINTR))
continue;
if (rcw < 0) {
perror("_write() failed");
break;
}
if (rcw == 0) {
fprintf(stderr, "Reached write EOF (?!)\n");
break;
}
if (rcw == 1) {}
}
break;
case 3 :
printf("case 3: transmit 1\n");
rcr = _read(fdr, bufr, numbyter);
if ((rcr < 0) && (errno == EINTR))
continue;
if (rcr < 0) {
perror("_read() failed");
break;
}
if (rcr == 0) {
fprintf(stderr, "Reached write EOF (?!)\n");
break;
}
file_write(bufr, rcr);
if (rcr == 40) {}
}
break;
I removed the logic in the rcr and rcw if statements since they are not relevant to xillybus. I am also inclusing the fifo mapping and enable logic on the fpga side although I do not believe this is the issue:

assign capture_en_rd = capture_open && !capture_full && (|pc_request) && !capture_select;
assign capture_en_wr = !request_empty;
fifo_write_1 en_fifo
(.rst(!user_w_write_32_open),
.wr_clk(bus_clk),
.rd_clk(clk),
.din(user_w_write_32_data),
.wr_en(user_w_write_32_wren),
.rd_en(capture_en_wr),
.dout(pc_request),
.full(user_w_write_32_full),
.empty(request_empty)
);
fifo_read_1 focused_fifo
(
.rst(!user_r_read_128_open),
.wr_clk(clk),
.rd_clk(bus_clk),
.din(capture_data),
.wr_en(capture_en_rd),
.rd_en(user_r_read_128_rden),
.dout(user_r_read_128_data),
.full(capture_full),
.empty(user_r_read_128_empty)
);
I appreciate the assistance

[support]

Hello,

You didn't show the code that allocates the memory for bufr. Could it be that you forgot doing that? In that case, bufr will be a null pointer, so that would definitely explain the error.

Regards,
Eli

[Guest]

Yes! that was it thank you

However the program is now getting stuck on the line: rcr = _read(fdr, bufr, numbyter);

I am allocating the memory like this:
size_t size = 128000;
unsigned char *bufr = malloc(size);
if (bufr == NULL) {
fprintf(stderr, "Memory Allocation Failed");
return 1;
}
Which is not returning any error so I believe that is fine,
I have a few questions to figure out where to start debugging

1. let's say there is no data in the stream, the _read() function would wait 10ms and then return a value of zero correct? or would it wait indefinitely until data is present?
2. How does xillybus handle sending data smaller than the width of the stream on the fpga side?
3. In my case when sending a value of of 0xFF using write, the file will interpret that as "ÿ" which the FPGA then reads as 11111111?
4. Can you have multiple streams open at the same time? for example xillybus_write_32 and xillybus_read_32 or can only one be open at a time?
5. I cannot remember if it says so in the documentation, but does adding debug cores interfere with the pcie communication?

[support]

Hello,

I'll take them one by one:

1. let's say there is no data in the stream, the _read() function would wait 10ms and then return a value of zero correct? or would it wait indefinitely until data is present?
2. How does xillybus handle sending data smaller than the width of the stream on the fpga side?
3. In my case when sending a value of of 0xFF using write, the file will interpret that as "ÿ" which the FPGA then reads as 11111111?
4. Can you have multiple streams open at the same time? for example xillybus_write_32 and xillybus_read_32 or can only one be open at a time?
5. I cannot remember if it says so in the documentation, but does adding debug cores interfere with the pcie communication?

1. If there's no data in the stream, _read() blocks indefinitely. Returning zero means EOF. If there is something to return, but less than the amount requested, _read() returns after 10ms.
2. If the amount of data doesn't complete a full word, Xillybus can't send it to the FPGA. Think about it -- what would the driver do when the next byte eventually arrives? So as in your case, when you send one byte to write_32 (?), nothing happens.
3. There is no question of interpretation. You send 0xff, you get 0xff at the other side. File streams deal with bytes and words, not ASCII characters.
4. The streams are completely independent. You can perform any operation at will in parallel, if you like (with different programs or threads).
5. Debug cores (such as ILA) don't interfere with anything, as far as I know.

Regards,
Eli

[Guest]

That all makes sense,

Thanks for all the help m8