I was following the xillycapture example in the FPGA designer guide document and noticed that the FIFOs in the demo bundle are still the default widths of 32bits and 8 bits while I have modified the bundle to the XL core with read widths of 128bits and write widths of 32bits.
Doing the speed test in the "Getting started with windows host" I have reached my desired speed and I am aware that there are a lot of intricacies on the back end so I was wondering if I should modify the FIFOs to match my read/write widths?
Thanks!
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