The Xillybus Forum

Hi,
how can I change bus_clk from 100MHz to a lower value on Zedboard?

Hello,

You probably don't want to go that path. It involves the following steps (at least, I might have missed something): Build the project on XPS, change the FPGA1 clock in the project's setting, derive the BSP from it, generate and compile the FSBL accordingly and recompile U-boot along with the new FSBL, and rebuild boot.bin accordingly. Then change the same clock's setting in the Vivado project (I suppose you work with Vivado?) and build the project as usual.

To get this working, you'll probably need to download the ISE suite (for XPS) and learn how to work with the ARM cross compiler.

So it's quite a long way to go.

Now, odds are that you want to reduce bus_clk because it fails to meet constraints on your own logic. That's easily solved: You may use dual-clock ("asynchronous") FIFOs instead of the single-clock FIFOs in the demo project. This allows you to work with any clock you like for your own logic, and connect that clock to the FIFO for driving the side that talks with your logic.

Just a word of notice: Assuming that you're working with Vivado, make sure to create clock group constraints for the two clocks, declaring that they're independent, or timing may fail based upon timing between the paths (which should be ignored).

Regards,
Eli

ok thank you!
I have to include my own asyncronous FIFO or there is already available on the demo bundle?

You need to add the FIFO as a new IP to the project.

Regards,
Eli

ok thank you.

Another question. If I use more read/write ports on Xillybus IP Core (so more FIFOs), I increase the bandwidth of my system?

Hello,

The bandwidth limit published for each platform is the total aggregate bandwidth of all streams at any given time. So adding more streams will not help you exceed that total.

Regards,
Eli

ok this means that, using only one FIFO between host and application logic, Xillybus automatically use the maximum bandwidth? And if I use 2 FIFOs, Xillybus divides the bandwidth between this two FIFO and so on?

Yes, there's a round-robin mechanism inside Xillybus' IP core that makes sure that no stream is starved from resources, so when there's pressure on bandwidth, you get the total maximal bandwidth divided among the active streams.

Regards,
Eli

ok. for zedboard the maximum bandwidth is 300MB/s right? as riported in the "Download Xillybus for PCIe". and so when I set "Expected BW" in the IP Core Factory, I have to divide this 300MB/s between all of my streams considering the effective bandwidth requirement of each stream? For example I can use 50MB/s for a stream, 40MB/s for another and so on.

What is the maximum number of streams I can use? and for zedboard is only available the revision A? there is no possibility to go further the 300MB/s?

thanks a lot!

Hello,

There is no practical limit for the number of streams you can use. It's a matter of the device getting full with the logic implementing it. The core has been tested for 60 streams or so, but there's probably no issue going higher (on devices that can take the load).

And indeed, there's only revision A cores for Zynq (in the PL/PS context), with 300 MB/s, which you'll need to divide between the streams you intend to use concurrently, yes. There's a chance you'll see higher figures in real tests, though.

And since we're into bandwidths, I suggest taking a look on this:

http://xillybus.com/doc/bandwidth-guidelines

Regards,
Eli